SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
The IrDA function generates interrupts. All interrupts can be enabled and disabled by writing to the appropriate bit in the interrupt enable register (UART_IER_IRDA). The interrupt status of the device can be checked by reading the interrupt identification register (UART_IIR_IRDA).
The UART, IrDA, and CIR modes have different interrupts in the UART module and, therefore, different UART_IER_IRDA and UART_IIR_IRDA mappings, depending on the selected mode.
The IrDA modes have eight possible interrupts (see Table 12-74). The interrupt line is activated when any interrupt is generated (there is no priority).
| IIR_IRDA Bit | Interrupt Type | Interrupt Source | Interrupt Reset Method |
|---|---|---|---|
| 0 | RHR interrupt | DRDY (data ready) (FIFO disabled) RX FIFO above trigger level (FIFO enabled) | Read the UART_RHR register until the interrupt condition disappears. |
| 1 | THR interrupt | TFE (UART_THR empty) (FIFO disabled) TX FIFO below trigger level (FIFO enabled) | Write to the UART_THR until the interrupt condition disappears. |
| 2 | Last byte in RX FIFO | Last byte of frame in RX FIFO is available to be read at the UART_RHR port. | Read the UART_RHR register. |
| 3 | RX overrun | Write to the UART_RHR register when the RX FIFO is full. | Read UART_RESUME register. |
| 4 | Status FIFO interrupt | Status FIFO triggers level reached. | Read STATUS FIFO. |
| 5 | TX status | UART_THR empty before EOF sent. Last bit of transmission of the IrDA frame occurred, but with
an underrun error OR Transmission of the last bit of the IrDA frame completed successfully. | Read the UART_RESUME register OR Read the UART_IIR_IRDA register. |
| 6 | Receiver line status interrupt | CRC, ABORT, or frame-length error is written into the STATUS FIFO. | Read the STATUS FIFO (read until empty - maximum of eight reads required). |
| 7 | Received EOF | Received end-of-frame | Read the UART_IIR_IRDA register. |