The DDR PHY provides a means to reduce the operational power when it is not actively transferring read or write data for an extended periond of time. This is done using the DFI low power interface. Using this interface, the DDR controller communicates to the PHY that it may enter its own low-power state and informs the PHY how quickly it requires the PHY to recover if a low-power state is entered. This DDR PHY has the following power modes:
- Idle: This is a period in which no read or write activity is being performed by the DDR controller. The PHY is not in any low power state, and is ready to accept commands at any time.
- Read/Write: This describes the time period when the PHY is actively performing a read or write operation triggered by the DDR controller.
- Light Sleep: This is a low-power state in
which the master delay lines and their logic receive a clock, but all other
slice logic is gated off. The PHY PLLs remain in an active state. Register
reads and writes to data and address slices are not permitted. The PHY
returns quickly to functional operation after an exit from light sleep.
After exiting the PHY initializes the slave delay settings automatically.
The master delay line macro maintains lock. This mode is entered if the
dfi_lp_wakeup signal is driven with a value less than or equal to the
programmed value in bits [3:0] of the the DDRSS_PHY_1318[15-8] PHY_LP_WAKEUP
field. If low power idle state is enabled, the value must also be greater
than the value of bits [7:4] in the DDRSS_PHY_1318[15-8] PHY_LP_WAKEUP
field.
- Deep Sleep: This is an ultra low-power
state in which clocking to the data, address, and address/control slices is
disabled. The PLLs are in a power down state. Pad calibration functions are
frozen. When in this mode, no DFI accesses or register reads and writes can
be performed. This mode is entered if the dfi_lp_wakeup signal is driven
with a value greater than the programmed value in bits [3:0] of the the
DDRSS_PHY_1318[15-8] PHY_LP_WAKEUP field.
- Low Power Idle: This is a low power
version of idle where the data slices are placed in a light sleep mode while
still allowing accesses to the data slice register address space. The
DDRSS_PHY_1318[16] PHY_LS_IDLE_EN bit enables this low power idle state. The
mode is entered if the dfi_lp_wakeup signal is driven with a value less than
or equal to the programmed value of bits [7:4] in the DDRSS_PHY_1318[15-8]
PHY_LP_WAKEUP field.
In general, if the SDRAM is placed into a power-down mode, the DDR PHY should enter light sleep. If the SDRAM is placed in a self-refresh mode, the DDR PHY could enter deep sleep.
The DDRSS_PHY_1319[9-0] PHY_LP_CTRLUPD_CNTR_CFG
field controls the number of clock controller cycles between de-assertion of the
dfi_lp_req signal and de-assertion of the dfi_lp_ack signal during exit of light
sleep and low power idle modes.
Within each data slice, the DQ, DM and DQS I/O's are disabled when not being written to or read from. The gate feedback pads are constantly enabled to control the read DQS gate open logic. The following fields control disabling the gate feedback pad for the corresponding slice during deep sleep mode:
- DDRSS_PHY_79[26-24] PHY_FDBK_PWR_CTRL_0
- DDRSS_PHY_335[26-24] PHY_FDBK_PWR_CTRL_1
- DDRSS_PHY_591[26-24] PHY_FDBK_PWR_CTRL_2
- DDRSS_PHY_847[26-24] PHY_FDBK_PWR_CTRL_3