Note: This chapter provides only a brief description of the GIC functionality and features. For more details on this module, refer to the Arm®CoreLink™ GIC-500 Generic Interrupt Controller Technical Reference Manual.
The Arm GIC-500 supports the following features in the device:
- Module revision: r1p1
- Supports all A72 cores
- 16 software generated interrupts (SGIs) per core
- 16 private peripheral interrupts (PPIs) per core
- 960 shared peripheral interrupts (SPIs)
- Locality-specific peripheral interrupts (LPIs), used for message-based interrupts
- Interrupt translation service (ITS)
- Device isolation
- ID translation for message-based interrupts
- This allows virtual machines to program devices directly
- Interrupt masking and prioritization
- Programmable, affinity-based interrupt routing
- 32 priorities for each interrupt
- Three different interrupt groups
- Group 0
- Non-secure group 1
- Secure group 1
Additionally, the GIC wrapper logic provides the following features:
- Synchronizes interrupt inputs to GIC clock
- Implements AXI2VBUSM and VBUSM2AXI bridges
- Used for bus protocol conversion (AXI-to-VBUSM and VBUSM-to-AXI, respectively)
- Implements an integrated ECC aggregator
- Only used to inject errors (for testing purposes)