SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
The DISPC has one clock domain for its internal logic and separate domains for each video port output.
The DISPC functional clock (DSS_FUNC_CLK) serves as the internal logic clock and also acts as the interface clock for the DISPC master and slave ports to system interconnect. There is no internal divider on this clock.
The DISPC pixel clocks (DSS_DPI_p_PCLK and DSS_DPI_p_DIV_PCLK, where p = 0 to 3 ) serve as the clocks for the output display interface. The DSS_DPI_p_PCLK clock is the 2x version of the DSS_DPI_p_DIV_PCLK clock. There are no internal dividers on the pixel clocks.
The relationship between the outgoing pixel clock and the input pixel clocks is as shown in Section 12.6.3.11.9.1, MSS Clocking Scheme.
The frequency of the display controller logic clock (DSS_FUNC_CLK) has to be greater than the frequency of the DSS_DPI_p_PCLK clocks, in order to get the DISPC internal logic to function properly. The frequency of the DSS_DPI_p_PCLK and DSS_DPI_p_DIV_PCLK clocks depend on the required output display resolution and frame rate. For information on the maximum supported frequency ratings, see the device-specific Datasheet.
The DSS_FUNC_CLK is asynchronous to DSS_DPI_p_PCLK and DSS_DPI_p_DIV_PCLK clocks. They can be generated by different sources.
The DSS_DPI_p_PCLK and DSS_DPI_p_DIV_PCLK clocks are synchronous to one another (for the same value of p).
The DSS0_COMMON_DSS_SYSCONFIG[0] AUTOCLKGATING regiser bit is set by default to allow the auto-gating of the interface and functional clocks. The AUTOCLKGATING bit can be reset to disable the auto-gating of the clocks, if required.
The DISPC provides also a clock-gating control on sub-module level, via configuration of the appropriate DSS0_COMMON_DISPC_CLKGATING_DISABLE register fields.