SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
LPDDR4 memories support data bus inversion (DBI) for signal integrity and power savings. The DDR controller can support DBI on the read or write path, or on both. DBI functions by ensuring that in each data byte, there are no more than four '1' bits. This can be used to confirm data transmission, and also for power savings.
DBI is controlled through the following:
Before enabling controller-level data bus inversion, the DBI mode must be enabled in the memories through a write to bits [7-6] of MR3. The system behavior depends on the value of the memory mode register bits, the DDRSS_CTL_291[16] RD_DBI_EN or DDRSS_CTL_291[8] WR_DBI_EN bit, and the value of each byte of data.
If the DDRSS_CTL_291[8] WR_DBI_EN bit is set to 1h, the user should ensure that the memory mode register WR DBI bit is also set to 1h. When both of these bits are set, the DDR controller examines each byte of the incoming write data and identifies the number of '1' bits within each byte. If a byte of data has 5 or more '1' bits, the DDR controller automatically flips the data bits in that byte and drives the dfi_wrdata_mask/dfi_wrdata_mask_p1 signal that corresponds to that byte to '1'. If the number of ‘1’ bits within a byte is 4 or less or the DDRSS_CTL_291[8] WR_DBI_EN bit is set to 0h, then the data is sent to the DRAMs unchanged. On the DRAM, if the dfi_wrdata_mask/dfi_wrdata_mask_p1 signal is driven to '1', the DRAM re-inverts that byte before storing the data and if the dfi_wrdata_mask/dfi_wrdata_mask_p1 signal is set to '0', the DRAM stores the data as received.
For the read path, if the memory mode register RD DBI bit is set to 1h, the DDRSS_CTL_291[16] RD_DBI_EN bit should also be set to 1h. When both of these bits are set, the DDR controller examines the input signal dfi_rddata_dbi_n/dfi_rddata_dbi_n_w1. If the signal is driven to '1' for a byte, the DDR controller inverts the associated byte before sending it to the requestor. If the dfi_rddata_ dbi_n/dfi_rddata_dbi_n_w1 signal is held to '0' for a byte, the data is sent out to the requestor unchanged.