SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
Table 8-17 shows all memory regions associated with the DDRSS0.
Region | Start Address | End Address | Region Size |
---|---|---|---|
DDRSS0 wrapper logic registers | 0x00 0298 0000 | 0x00 0298 01FF | 512 B |
DDR controller registers | 0x00 0299 0000 | 0x00 0299 1FFF | 8 KB |
DDR PHY independent module registers | 0x00 0299 2000 | 0x00 0299 3FFF | 8 KB |
DDR PHY registers | 0x00 0299 4000 | 0x00 0299 7FFF | 16 KB |
DDRSS0_ECC_AGGR_CTL registers | 0x4D 200B 0000 | 0x4D 200B 03FF | 1 KB |
DDRSS0_ECC_AGGR_VBUS registers | 0x4D 200B 0400 | 0x4D 200B 07FF | 1 KB |
DDRSS0_ECC_AGGR_CFG registers | 0x4D 200B 0800 | 0x4D 200B 0BFF | 1 KB |
External SDRAM data space - region 0 (32-bit low memory space) | 0x00 8000 0000 | 0x00 FFFF FFFF | 2 GB |
External SDRAM data space - region 1 (high memory space)(1) | 0x08 0000 0000 | 0x09 FFFF FFFF | 8 GB |