SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
Figure 6-46 shows the MCSPI controller ability to delay the first MCSPI word transfer to give time for system to complete some parallel processes or fill the FIFO in order to improve transfer bandwidth. This delay is applied only on first MCSPI word after MCSPI channel enabled and first write in transmit register. It is based on output clock frequency.
This option is meaningful in controller mode and single channel mode asserted through MCSPI_MODULCTRL[0] SINGLE.
Few delay values are available: No delay, 4/8/16/32 MCSPI cycles.
Its accuracy is half cycle in clock bypass mode and depends on clock polarity and phase.