I3C devices shipped with Static Address can be enumerated prior to DAA procedure using SETDASA CCC command. In order to enumerate I3C device firmware needs to follow procedure:
- Prepare device's retaining register:
- Write corresponding I3C_DEV_IDn_RR0 (offset 0x080 + (n × 0x010)) for n = 0 to 11:
- I3C_DEV_IDn_RR0[9] IS_I3C (n = 0 to 11): 0x01
- I3C_DEV_IDn_RR0[7-0] DEV_ADDR bit-field (n = 0 to 11): set to device's Static Address for [7-1] bits and set to Static Address parity for bit 0
- Issue SETDASA CCC:
- Make sure that controller is enabled.
- Write new Dynamic Address to TX FIFO.
- Write Command Word1 with SETDASA CCC value:
- I3C_IMD_CMD1[7-0] CCC bit-field: 0x87
- Write Command Word0 with following field values:
- I3C_CMD0_FIFO[30] IS_CCC bit: 0x01
- I3C_CMD0_FIFO[23-12] PL_LEN bit-field: 0x01
- I3C_CMD0_FIFO[7-1] DEV_ADDR bit-field: Static
Address
- I3C_CMD0_FIFO[0] RNW bit: 0x00
- Enable at least COMP, NACK and INVALID_DA interrupts by writing 0h to IER register.
- Wait for COMP interrupt (read I3C_MST_ISR).
- If COMP and no other interrupt occurs, continue. Otherwise, handle the error situation.
- Fill Dynamic Address into device configuration register:
- Modify I3C_DEV_IDn_RR0 (offset 0x080 + (n × 0x010)) for n = 0 to 11 register by writing Dynamic Address to DEV_ADDR field and its parity to ADDR_PAR field (keep values of other fields)
- If not already known to application host, retrieve BCR with GETBCR CCC:
- Write Command Word1 with GETBCR CCC value:
- I3C_IMD_CMD1[7-0] CCC bit-field: 0x8E
- Write Command Word0 with following field values:
- I3C_CMD0_FIFO[30] IS_CCC bit: 0x01
- I3C_CMD0_FIFO[23-12] PL_LEN bit-field: 0x01
- I3C_CMD0_FIFO[7-1] DEV_ADDR bit-field: Dynamic
Address
- I3C_CMD0_FIFO[0] RNW bit: 0x01
- Wait for COMP interrupt
- Read RX FIFO register - BCR is stored in bits [7:0]
- Optionally retrieve Provisional ID and DCR with corresponding CCCs:
- Write Command Word1 with GETDCR CCC value:
- I3C_IMD_CMD1[7-0] CCC bit-field: 0x8F
- Write Command Word0 with following field values:
- I3C_CMD0_FIFO[30] IS_CCC bit: 0x01
- I3C_CMD0_FIFO[23-12] PL_LEN bit-field: 0x01
- I3C_CMD0_FIFO[7-1] DEV_ADDR bit-field: Dynamic
Address
- I3C_CMD0_FIFO[0] RNW bit: 0x01
- Wait for COMP interrupt
- Read RX FIFO register - DCR is stored in bits [7:0]
- Write Command Word1 with GETPID CCC value:
- I3C_IMD_CMD1[7-0] CCC bit-field: 0x8D
- Write Command Word0 with following field values:
- I3C_CMD0_FIFO[30] IS_CCC bit: 0x01
- I3C_CMD0_FIFO[23-12] PL_LEN bit-field: 0x06
- I3C_CMD0_FIFO[7-1] DEV_ADDR bit-field: Dynamic
Address
- I3C_CMD0_FIFO[0] RNW bit: 0x01
- Wait for COMP interrupt
- Read RX FIFO register twice – PID bytes are stored in two FIFO locations. See Table 12-29
- Write retrieved device configuration data to retaining registers:
- Write four MSB of obtained PID value into I3C_DEV_IDn_RR1 (offset 0x084 + (n × 0x010)) for n = 0 to 11:
- Write two LSB of obtained PID value as well as BCR and DCR values into I3C_DEV_IDn_RR2 (offset 0x088 + (n × 0x010)) for n = 0 to 11:
Note: SETDASA CCC command has advantage over DAA in shorter time spent on device configuration as retrieving PID and DCR (6 + 1 bytes transmitted over I3C bus) is optional and can be skipped if not used.