SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
This is the High Speed (HS) mode where the eMMC CLK is set to 50 MHz. To emulate the Interface timing, a Hold time is inserted on Transmit data lines by using the Phase shifted Tx Clock. The amount of phase shift can be from 1 to 16 Taps. In this mode, the TX Clock Phase shift is being performed by using one of the first 16-taps of the DLL TXCLK Phases. The Phase shifting on the RX path is disabled in this mode.