Each CTRL_MMR module has an associated
ACCESS_ERR_0 interrupt request. The interrupt requests are assocaited with the
following registers:
- INTR_RAW_STATUS — interrupt
raw status register
- INTR_ENABLED_STATUS_CLEAR —
interrupt status register
- INTR_ENABLE — interrupt
enable register
- INTR_ENABLE_CLEAR — interrupt
disable register
The following applies for the interrupt behavior
of each CTRL_MMR module:
- The CTRL_MMR module asserts
its interrupt line only if the interrupts are enabled by setting to 1h the
corresponding bits in the INTR_ENABLE register. These interrupts can be
disabled by setting to 1h the corresponding bits in the INTR_ENABLE_CLEAR
register.
- After an interrupt has been
serviced, software must clear the corresponding status flag. This is done by
setting to 1h the corresponding bit in the INTR_ENABLED_STATUS_CLEAR
register which also clears the corresponding bit in the INTR_RAW_STATUS
register. The status flags in the INTR_RAW_STATUS register are set even if
the corresponding interrupt is disabled unlike those in the
INTR_ENABLED_STATUS_CLEAR register, which are set only if the corresponding
interrupt is enabled.
- An interrupt is also
generated by the CTRL_MMR, if certain bit in the INTR_RAW_STATUS register is
set to 1h and the corresponding interrupt is enabled through the INTR_ENABLE
register. This feature is useful during user software debugging. In
addition, even if interrupts are not enabled the corresponding raw flag in
the INTR_RAW_STATUS register is set to 1h when an IRQ condition occurs.
- Even if interrupts are not
enabled, a status bit in the INTR_RAW_STATUS register can also be cleared by
setting to 1h the corresponding bit in the INTR_ENABLED_STATUS_CLEAR
register.
Table 5-4 lists the
interrupt events which can assert the (ACCESS_ERR_0) interrupt lines.
Table 5-4 CTRL_MMR Events
Event |
Description |
PROXY_ERR |
Proxy violation interrupt. Occurs when a write is
attempted through the Proxy0 address of register whose associated
CLAIM bit is set. |
LOCK_ERR |
Lock violation interrupt. Occurs when writing to a
register in a locked CTRL_MMR partition. |
ADDR_ERR |
Addressing violation interrupt. Occurs when
accessing an illegal address inside the CTRL_MMR module. |
PROT_ERR |
Protection violation interrupt. Occurs when a
register is accessed without the required secure/privilege level
permissions. |
When an error event as described in Table 5-4 occurs,
the error associated details are captured in the FAULT_ADDRESS, FAULT_TYPE_STATUS
andFAULT_ATTR_STATUS registers. FAULT_ADDRESS contains the address of the first
fault access. FAULT_TYPE_STATUS andFAULT_ATTR_STATU contain status attributes
associated with the first fault access. To clear the contents of these three
registers and allow them to latch the attributes of the next fault the
FAULT_CLEAR[0] CLEAR bit must be set to 1h.