SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
For each MCU_R5FSS0 CPU, the interface clock is an integer ratio of the CPU0 clock. The exact core to interface clock ratio is configured via associated Control Module register:
The interface clock has a fixed frequency, so this register is essentially used to select the CPU clock frequency. Due to some design limitation, the core frequency switch for the MCU_R5FSS0 may cause clock misalignment. To avoid this this clock misalignment, the below software sequence should be implemented by a core other than MCU_R5FSS0_CORE0 or MCU_R5FSS0_CORE1 when changing the CPU clock frequency:
Note that the sequence above is a static configuration change and any context in the MCU_R5FSS0 will be not be preserved. There is no dynamic clock reconfiguration available.