The data routing unit (DRU) is a high bandwidth, flexible routing engine with programmable DMA transfer requests. It enables user to perform high speed data transfers between memory mapped slave endpoints, processor caches and shared caches. DRU behaves like a DMA transfer controller, moving data at CPU frequency.
The DRU supports the following features:
- Programmable configuration registers for direct transfer request submission
- A dedicated atomic register set that requires entire TR sent in a single burst
- Three nonatomic register sets that allow TR to be written in separate burst and a write to the SUBMIT_WORD0 register triggers the TR
- Read and write command queues
- Five different queues with a split arbitration between fixed priority and round robin arbitration
- Each channel can be configured to go to one of these queues
- Programmable priority for each queue
- Allows setting priority for commands relative to other masters in the system
- One dedicated read port and one dedicated write port to generate independent read and write commands
- Generates one read command every cycle
- Generates one write data phase every cycle
- Moves the data at CPU frequency
- Optimizes transfers up to 128 byte boundaries
- Support for triggers to gate levels of the DMA loop
- Supports one dedicated local trigger
- Supports two dedicated external global triggers from the PSI-L
- All triggers can be overwritten and controlled by software instead of hardware based event
- Support for region based and channelized firewall
- Region based firewall intended to protect DRU configuration registers within a programmatically specified range
- Channelized firewall that protects:
- The real time configuration registers for each channel
- The TR submission registers for each channel
- The data transfers for each channel
- Data formatting networks
- Circular addressing support for one side of the transfer
- Independent 48-bit address fields for source and destinations
- Up to four dimensional data transfers
- Has independent source and destination index for up to four dimensional transfers
- Error Handling
- Debug support through memory mapped registers
- Data transfer error reports
- Error detection and Correction
- Full SEC/DED support for the incoming data
- Full SEC/DED protection each entry in the TR queues
- Single bit parity support for each 32-bit word in the data buffer
- Parity protection for the address
- PSI-L Interface
- Receive requests for pre-warm of L2 or L3 Cache
- Receive TR requests from the UDMA
- Send response TRs
- Receive data from a remote UTC
- Send data to a remote UTC
- Maintains 2D formatting across PSI-L if requested in TR
- Feature enhancements for DRU R30:
- IO memory management unit and micro-TLB
- Features integrated uTLB (Translation Look aside
Buffer)
- Supports virtual addresses and physical addresses in TR
requests
- A read and write uTLB with 2 entries per uTLB
- Communicates through PSI-L to IOMMU
- Compression and Decompression
Unsupported features:
- Transpose data between source and destination memory to memory
transfers