SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
Figure 12-152 depicts a simplified internal block diagram of the CSI_RX_IF and its surroundings.
The CSI2 core streams 4 channels of data to the several export paths.
Stream0 (high BW DMA up to 32 channel contexts) streams 32-bits worth of data, that is re-formatted and sent as pixel format into 128 bits as PSIL data. There are 32 sets of MMRs/Registers that map virtual channels and data type to PSIL threads. Data is sent out PSIL in FIFO order as it is received. There is no priority. Data re-formatting is done to end up with correct data organization in memory so that other ip can use the data. The data type must be configured in MMRs to ensure proper reformatting. See Section 12.7.1.3.5. The large buffer of PSIL data (2048x128) has ECC protection, see Section 12.7.1.3.7
Stream1 (unlimited channel contexts, minimal buffering) streams an optional loopback output to CSI_TX_IF controller for diagnostic check.