SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
The Error Correcting Code (ECC) is a mechanism for providing increased system reliability (via reduction of memory soft errors) by allowing single bit errors to be detected and corrected and double bit errors to be detected.
The ECC Aggregator provides a single EOI-handshake based interrupt to the host (for both single and double error detections).
The ECC Aggregator will write 0’s to all of memory after reset is released. The ADC_SEQUENCER_STAT[6] MEM_INIT_DONE bit will be 0 during this period and will be set to 1 upon completion.
For more information about the ECC Aggregator, see ECC Aggregator and ADC ECC Registers.
See also Testing ECC Error Injection and ADC ECC Registers.