SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
(1) If S18A of CMD5 or S18A of ACMD41 is set to 1, signal voltage switch is performed according to the following steps. Otherwise, exits from this procedure.
(2) Issue CMD11.
(3) Check response and if an error is detected, go to step (12).
(4) Stop providing SD clock to the card.
(5) Check DAT[3:0] level. If the level is 0000b, the card is ready to start voltage switch sequence. Otherwise, go to (12) to quit the sequence.
(6) Set MMCSD0_HOST_CONTROL2[3] V1P8_SIGNAL_ENA bit.
(7) Wait 5 ms. 1.8 V voltage regulator shall be stable within this period.
(8) If MMCSD0_HOST_CONTROL2[3] V1P8_SIGNAL_ENA bit is cleared by Host Controller, go to step (12).
(9) Provide SD Clock to the card again.
(10) Wait 1 ms.
(11) Check DAT[3:0] level. If the level is 1111b, switch to 1.8 V signal level is completed successfully. Otherwise, go to (12).
(12) If an error occurs during voltage switch procedure, stop providing the power to the card. In this case, Host Driver should retry initialization procedure by setting S18R to 0 at step (7) and (21) in Figure 12-120 and Figure 12-121.