SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
As is specified in the TI DMA Architecture specification, the host initiates a Tx DMA channel teardown operation by writing to the TDOWN bit in the TCHANRT UDMA_TRT_CTL_j register. Once a channel teardown is requested, the appropriate Tx DMA unit will complete any packet/TRs that the channel has prefetched or is currently in the process of transferring and will then clear the EN bit, will send a Teardown packet out the outbound Payload Data PSI-L interface, and will push a Teardown Completion Record onto the Tx Default Queue for the channel. If the Tx DMA engine is not currently in a packet/TR for the channel, it will immediately clear the EN, send the Teardown packet, and push the Teardown Completion Record. Once the teardown is complete, no further packet processing will occur until the host software re-enables the channel.