SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
Figure 10-14 illustrates the event and interrupt flow within the NAVSS and output interrupts to a CPU. Information that flows between NAVSS modules is also indicated (in this case, Global Event (GE) information flows between ring accelerator and the PSILSS).