SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
The DISPC DMA controller is based on a 5-channel DMA engine that:
The DISPC DMA engine has an additional (secondary) 128-bit master port. By default, all transactions from every channel go through the primary 128-bit master port. If compression is enabled for a particular channel (by using the FBDC module), then all the transactions of that channel go through the secondary master port. It is also possible to force transactions from a particular channel to the secondary master port (even without compression) by setting the DSS0_VID_ATTRIBUTES2[25] MPORTSEL register bit to 0x1. This is possible only when compression through the FBDC is completely disabled (that is, none of the read channels are fetching compressed data).
Each pipeline has a dedicated DMA buffer and channel with independent settings. If a pipeline is disabled (that is, not used), then its DMA buffer can be assigned to another pipeline by configuring the DSS0_COMMON_DISPC_GLOBAL_BUFFER register. For example, unused buffers for a VIDL pipeline can be used by a VID pipeline.
Each DMA channel supports a total of 8 line buffers, each of which can store 2048 32-bit pixels.
The DMA engine fetches encoded pixels from the system memory only when the video layer is enabled (a valid configuration has been programmed for the video layer), that is, when the video window is present and the video pipeline is active.