SPRUJ28 User guide

SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1

5.5.22.2 McASP Integration Details

AHCLKX and AHCLKR Clock Sources

The McASP AHCLKX and AHCLKR inputs may be driven either by device clock input pins (those with associated AHCLK clock muxing) or by the ATL output clocks. The AHCLKX and AHCLKR outputs do not have explicit output pins. Instead the device AUDIO_EXT_REFCLK[1:0] pins may be driven either by the associated McASP AHCLK outputs or by the ATL output clocks. See the clocking section for details.

Cross-McASP Synchronization using Frame Sync Feedback

In order to align frame syncs across McASPs that may be feeding DACs with different formats but the same frequency, the frame sync of McASPx can be optionally fed into a receive data pin of McASPy. The device includes a multiplexor to allow any McASP transmit or receive frame syn to be connected to receive channels 14 & 15 of any other McASP:

If this serializer is enabled as a receiver, then the frame sync of McASPx will appear as receive data for McASPy. For example, with both McASPs configured for 16-bit data, 2 slots, one might make the conclusions shown in the table below based on receive data. Note that the purpose here is not to actually 'receive' the accurate frame sync as data that is processed. Rather, it is to inspect the relative timing of the frame syncs, and then make an adjustment to the width of the bit clock of McASPx until perfect (ex. #4 from Table 31-9) or good enough alignment (ex. #3, #5) is achieved.

To adjust the McASP transmit bit clock, the CLKADJ bits 17:16 of the ACLKXCTL register can be used to lengthen (write 2'b10) or reduce (write 2'b01) the McASP bit clock period in a one-shot fashion. After each adjustment the frame sync should be checked again and the process repeated until the two frame syncs are aligned. For example, if McASPy frame sync is leading McASPx frame sync, the expectation would be to write 2'b01 to McASPx's CLKADJ bits, which will shorten one bit clock period of McASPx and cause the next frame sync to occur one input clock cycle earlier (input clock to McASP internal transmit clock divider). This would be repeated until the two Frame Syncs are within optimal alignment.

This process is expected to be carried out once, before any audio transfers occur. It is not intended to be used for sample rate conversion but rather initial phase alignment of transmit data across McASPs. It should also be noted that exact alignment as represented in the table may not actually be ideal. For example, there may be filtering delay inside the DACs that are fed by the McASPs. If the filter delay between two DACs is different, an offset in alignment of the frame syncs may actually be what is needed to align the analog audio output across channels. One positive of this mechanism is that any arbitrary alignment of frame sync signals can be achieved to within +/- 1 bit clock by adjusting the target value for the "Received At McASPy" column.

Sample	Received at McASPy	Alignment Conclusion (assumes active low frame sync)
1	1110_0000_0000_0000_0001_1111_1111_1111	Frame Sync of McASPy Leads Frame Sync of McASPx Slightly
2	0000_0000_0000_0011_1111_1111_1111_1100	Frame Sync of McASPy Lags Frame Sync of McASPx Slightly
3	1000_0000_0000_0000_0111_1111_1111_1111	Frame Syncs are aligned to within +/- 1 Bit Clock
4	0000_0000_0000_0000_1111_1111_1111_1111
5	0000_0000_0000_0001_1111_1111_1111_1110

Enhanced Display Port Audio

Note that the eDP uses McASP4 AXR[3:0] exclusively to provide audio data to the DisplayPort interface. If the eDP function is not required, McASP4 is available for general usage.