SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
Poll the I2C_IRQSTATUS_RAW [4] XRDY bit, or use the XRDY interrupt (the I2C_IRQENABLE_SET [4] XRDY_IE bit must be set to 1) to write data to the I2C_DATA register.
If the transfer length does not equal the TX FIFO threshold (the I2C_BUF[5-0] TXTRSH bit field + 1), use the draining feature (enable the XDR interrupt by setting the I2C_IRQENABLE_SET [14] XDR_IE bit to 1).
In transmit mode only, the I2C_IRQSTATUS_RAW [10] XUDF bit indicates whether the transmitter has experienced underflow.
In controller transmit mode, underflow occurs when the shift register and the TX FIFO are empty and there are still some bytes to transmit (the value of the I2C_CNT[15-0] DCOUNT bit field is not 0).
In target transmit mode, underflow occurs when the shift register and the TX FIFO are empty and the external I2C controller device still requests data bytes to be read.
The I2C_IRQSTATUS_RAW [7] AERR bit is set to 1 when a write access is performed in the I2C_DATA register while the TX FIFO is full. The corresponding interrupt can be enabled by setting the I2C_IRQENABLE_SET [7] AERR_IE bit to 1.