Figure 6-152 presents VPAC block diagram.
It consists of four hardware module blocks and three infrastucture module blocks.
VPAC hardware blocks:
- LDC (Lens Distortion Correction): LDC hardware block reads data from memory (DDR or on-chip) and applies perspective transform as well as correction of lens distortion (including fisheye lens). The output of LDC block can be sent to external memory (DDR) or sent to other hardware module (Scalar, Noise filter) for further pre-processing via local shared memory (SL2).
- Scalar (or Downsampler or Resizer): Scalar hardware block reads data from memory (DDR or on-chip) to shared memory (SL2) and generates up to 10 scaled output from two inputs with varios scaling ratios (between × and ×0.25). The output of Scalar block can be sent to external memory (DDR) from shared memory (SL2) or can be further noise filtered using Noise filter hardware.
- Noise Filter (NF): NF hardware block reads data from memory (DDR or on-chip) to shared memory (SL2) and does Bilateral filtering to remove noise. The output of NF block can be sent to external memory (DDR) from shared memory (SL2) or can be further re-sized using Scalar hardware.
- VISS (Vision ISS): There are two instances of on-the-fly processing for sensor related processing in VISS hardware.
VPAC infrastucture blocks:
- Shared Level 2 (SL2) memory: It is used to exchanging data across hardware module block (for example: LDC, Scalar and NF) as well as to DMA engine (for example: UDMA).
- Hardware Thread Scheduler (HTS): It is used for IPC communication among various hardware module block for example: LDC, Scalar and NF) as well as to DMA engine (for example: UDMA).
- DMA engine (UDMA consisting of CC + DRU) is inside VPAC boundary. It consists of one CC and two TC.