The PDMA5 module supports the following features:
- Implements CPPI 5.0 compliant third-party Unified Transfer Controller (UTC)
- Provides 1 memory write access unit (write unit 0):
- Provides a 32-bit wide VBUSP write-only master interface for peripheral accesses.
- Supports write bursts up to 64 bytes (on selected channel types)
- Provides 1 memory read access unit (read unit 0)
- Provides a 32-bit wide VBUSP read-only master interface for peripheral accesses
- Supports read burst up to 64 bytes (on selected channel types)
- Supports 1 outstanding read
- Supports up to 54 simultaneous destination (Tx) channels
- Supports up to 54 simultaneous source (Rx) channels
- Supports static transfer requests (TR) only
- Supports MCAN transfer mode only (does not support X-Y and AASRC)
- Provides per-channel buffering:
- Provides 8×128-bit word deep data FIFO for each destination channel
- Provides 8×128-bit word deep data FIFO for each source channel
- Provides 128-bit wide PSI-L compliant data interface to remote UDMA-P and remote peripherals
- Provides 128-bit wide PSI-L compliant data interface from remote UDMA-P and remote peripherals
- Provides ECC support