SPRUJ40C may   2022  – may 2023

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1EVM Revisions and Assembly Variants
  5. 2System Description
    1. 2.1 Key Features
      1. 2.1.1 Thermal Compliance
      2. 2.1.2 Processor
      3. 2.1.3 Power Supply
      4. 2.1.4 Memory
      5. 2.1.5 JTAG/Emulator
      6. 2.1.6 Supported Interfaces and Peripherals
      7. 2.1.7 Expansion Connectors/Headers to Support Application Specific Add‐On Boards
    2. 2.2 Functional Block Diagram (SK-AM62 and SK-AM62B)
    3. 2.3 Functional Block Diagram (SK-AM62-P1 and SK-AM62B-P1)
    4. 2.4 AM62x SKEVM Interface Mapping
    5. 2.5 Power ON/OFF Procedures
      1. 2.5.1 Power-On Procedure
      2. 2.5.2 Power-Off Procedure
      3. 2.5.3 Power Test Points
    6. 2.6 Peripheral and Major Component Description
      1. 2.6.1  Clocking
        1. 2.6.1.1 Peripheral Ref Clock
      2. 2.6.2  Reset
      3. 2.6.3  OLDI Display Interface
      4. 2.6.4  CSI Interface
      5. 2.6.5  Audio Codec Interface
      6. 2.6.6  HDMI Display Interface
      7. 2.6.7  JTAG Interface
      8. 2.6.8  Test Automation Header
      9. 2.6.9  UART Interface
      10. 2.6.10 USB Interface
        1. 2.6.10.1 USB 2.0 Type A Interface
        2. 2.6.10.2 USB 2.0 Type C Interface
      11. 2.6.11 Memory Interfaces
        1. 2.6.11.1 DDR4 Interface
        2. 2.6.11.2 OSPI Interface
        3. 2.6.11.3 MMC Interfaces
          1. 2.6.11.3.1 MMC0 - eMMC Interface
          2. 2.6.11.3.2 MMC1 - Micro SD Interface
          3. 2.6.11.3.3 MMC2 - Wilink Interface
        4. 2.6.11.4 EEPROM
      12. 2.6.12 Ethernet Interface
        1. 2.6.12.1 CPSW Ethernet PHY 2 Default Configuration
        2. 2.6.12.2 CPSW Ethernet PHY 1 Default Configuration
      13. 2.6.13 GPIO Port Expander
      14. 2.6.14 GPIO Mapping
      15. 2.6.15 Power
        1. 2.6.15.1 Power Requirements
        2. 2.6.15.2 Power Input
        3. 2.6.15.3 Power Supply
        4. 2.6.15.4 Power Sequencing
        5. 2.6.15.5 AM62x SoC Power
        6. 2.6.15.6 Current Monitoring
      16. 2.6.16 AM62x SKEVM User Setup/Configuration
        1. 2.6.16.1 EVM DIP Switches
        2. 2.6.16.2 Boot Modes
        3. 2.6.16.3 User Test LEDs
      17. 2.6.17 Expansion Headers
        1. 2.6.17.1 PRU Connector
        2. 2.6.17.2 User Expansion Connector
        3. 2.6.17.3 MCU Connector
      18. 2.6.18 Interrupt
      19. 2.6.19 I2C Address Mapping
  6. 3Known Issues and Modifications
    1. 3.1  Issue 1 - HDMI/DSS Incorrect Colors on E1
    2. 3.2  Issue 2 - J9 and J10 Header Alignment on E1
    3. 3.3  Issue 3 - USB Boot descoped on E1
    4. 3.4  Issue 4 - OLDI Connector Orientation and Pinout
    5. 3.5  Issue 5 - Bluetooth descoped on E2 EVMs
    6. 3.6  Issue 6 - Ethernet PHY CLK Skew Default Strapping Changes
    7. 3.7  Issue 7 - TEST_POWERDOWN changes
    8. 3.8  Issue 8 - MMC1_SDCD spurious interrupts
    9. 3.9  Issue 9 - PD Controller I2C2 IRQ Not Pinned Out
    10. 3.10 Issue 10 - INA Current Monitor Adress Changes
    11. 3.11 Issue 11 - Test Automation I2C Buffer Changes
  7.   Regulatory Compliance
  8.   Revision History

2.6.17.3 MCU Connector

AM62x SKEVM has a 14x2 standard 0.1” spaced MCU connector which includes signals connected to the MCU Domain of SoC. 13 Signals include MCU_I2C0, MCU_UART0 (with flow control), MCU_SPI0 and MCU_MCAN0 signals are connected to the MCU Header. Additional control signals provided on the Header include CONN_MCU_RESETz, CONN_MCU_PORz, MCU_RESETSTATz, MCU_SAFETY_ERRORn, 3.3 V IO and GND. MCU_UART0 signals from AM62x SoC are connected to both MCU Header and FT4232 Bridge through MUX Mfr Part # SN74CB3Q3257PWR. The MCU Header does not include the Board ID memory interface. Allowed current limit is 100 mA on 3.3 V rail.

GUID-C1E3DDB0-C505-4558-9E46-D1B88B3187A8-low.png
Table 2-26 Pin MCU Connector (J9)
Pin No. SoC Ball No. Net Name Pin Multiplexed Signal
1 - VCC_3V3_SYS
2 - DGND
3 - NC
4 C9 MCU_SPI0_D1 MCU_SPI0_D1/MCU_GPIO0_4
5 - NC
6 D9 MCU_SPI0_D0 MCU_SPI0_D0/MCU_GPIO0_3
7 - DGND
8 B8 MCU_SPI0_CS1 MCU_SPI0_CS1/MCU_OBSCLK0/MCU_SYSCLKOUT0/MCU_EXT_REFCLK0/MCU_TIMER_IO1/MCU_GPIO0_1
9 - NC
10 E5 MCU_GPIO0_15 MCU_MCAN1_TX/MCU_TIMER_IO2/MCU_SPI1_CS1/MCU_EXT_REFCLK0/MCU_GPIO0_15
11 D4 MCU_GPIO0_16 MCU_MCAN1_RX/MCU_TIMER_IO3/MCU_SPI0_CS2/MCU_SPI1_CS2/MCU_SPI1_CLK/MCU_GPIO0_16
12 A6 MCU_UART0_CTS_CONN MCU_UART0_CTSn/MCU_TIMER_IO0/MCU_SPI1_D0/MCU_GPIO0_7
13 B5 MCU_UART0_RXD_CONN MCU_UART0_RXD/MCU_GPIO0_5
14 - NC
15 - DGND
16 D6 MCU_MCAN0_TX MCU_MCAN0_TX/WKUP_TIMER_IO0/MCU_SPI0_CS3/MCU_GPIO0_13
17 B6 MCU_UART0_RTS_CONN MCU_UART0_RTSn/MCU_TIMER_IO1/MCU_SPI1_D1/MCU_GPIO0_8
18 A7 MCU_SPI0_CLK MCU_SPI0_CLK/MCU_GPIO0_2
19 A5 MCU_UART0_TXD_CONN MCU_UART0_TXD/MCU_GPIO0_6
20 - DGND
21 D10 MCU_I2C0_SDA MCU_I2C0_SDA/MCU_GPIO0_18
22 B3 MCU_MCAN0_RX MCU_MCAN0_RX/MCU_TIMER_IO0/MCU_SPI1_CS3/MCU_GPIO0_14
23 B12 MCU_RESETSTATz MCU_RESETSTATz/MCU_GPIO0_21
24 A8 MCU_I2C0_SCL MCU_I2C0_SCL/MCU_GPIO0_17
25 E11 CONN_MCU_RESETz MCU_RESETz
26 D1 MCU_SAFETY_ERRORz_3V3 MCU_ERRORN
27 - DGND
28 D2 CONN_MCU_PORz MCU_PORz