SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
This register controls the default burst size of EDMA TPTC.
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Instance Name | Physical Address |
---|---|
MSS_CTRL | 50D0 0800h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TPTC_DBS_CONFIG_TPTC_A1 | RESERVED | TPTC_DBS_CONFIG_TPTC_A0 | ||||
NONE | R/W | NONE | R/W | ||||
0h | 0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:6 | RESERVED | NONE | 0h | Reserved |
5:4 | TPTC_DBS_CONFIG_TPTC_A1 | R/W | 0h | DBS [default burst size] tieoff value for TPTC A1. DBS tieoff defines optimally sized cmd.Both the read and write controller will always issue commands that are less than or equal to the DBS tieoff value. This will typically be on the order of 4 or 8 dataphases worth of data. DBS must always be tied off to no larger than half of the Channel FIFO size. Set DBS to - 2'b00 = 16 byte 2'b01 = 32 byte 2'b10 = 64 byte 2'b11 = 128 byte |
3:2 | RESERVED | NONE | 0h | Reserved |
1:0 | TPTC_DBS_CONFIG_TPTC_A0 | R/W | 0h | DBS [default burst size] tieoff value for TPTC A0. DBS tieoff defines optimally sized cmd.Both the read and write controller will always issue commands that are less than or equal to the DBS tieoff value. This will typically be on the order of 4 or 8 dataphases worth of data. DBS must always be tied off to no larger than half of the Channel FIFO size. Set DBS to - 2'b00 = 16 byte 2'b01 = 32 byte 2'b10 = 64 byte 2'b11 = 128 byte |