SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

2.2.74.1 MSS_CTRL_CPSW_CONTROL Register (Offset = 810h) [reset = 1000100h]

Ther register is for the CPSW Ethernet modes and additional controls on the.

Table 2-149 Instance Table

Instance Name	Physical Address
MSS_CTRL	50D0 0810h

Figure 2-74 MSS_CTRL_CPSW_CONTROL Name Register

Table 2-150 MSS_CTRL_CPSW_CONTROL Register Field Descriptions

Bit	Field	Type	Reset	Description
31:25	RESERVED	NONE	0h	Reserved
24	CPSW_CONTROL_RGMII2_ID_MODE	R/W	1h	Internal delay mode for port 2. Only for TX 1'b0 ID mode is disabled 1'b1 ID mode is enabled
23	RESERVED	NONE	0h	Reserved
22	CPSW_CONTROL_RMII2_REF_CLK_SEL	R/W	0h	To select the rmii_ref_clk loopback mux output either from PAD or from MSS_RCM. Write 1'b0 to get clock will be from IO pad[pad loopback]. Write 1'b1 to get clock from internal loopback.
21	RESERVED	NONE	0h	Reserved
20	CPSW_CONTROL_RMII2_REF_CLK_OE_N	R/W	0h	RMII_REF_CLK IO Output enable control 1'b0: Output enable 1'b1: Output Disable
19	RESERVED	NONE	0h	Reserved
18:16	CPSW_CONTROL_PORT2_MODE_SEL	R/W	0h	Port 2 Interface 3'b000 = MII 3'b001 = RMII 3'b010 = RGMII 011 - 111 = Not Supported
15:9	RESERVED	NONE	0h	Reserved
8	CPSW_CONTROL_RGMII1_ID_MODE	R/W	1h	Internal delay mode for port 1. Only for TX 1'b0 ID mode is disabled 1'b1 ID mode is enabled
7	RESERVED	NONE	0h	Reserved
6	CPSW_CONTROL_RMII1_REF_CLK_SEL	R/W	0h	To select the rmii_ref_clk loopback mux output either from PAD or from MSS_RCM. Write 1'b0 to get clock will be from IO pad[pad loopback]. Write 1'b1 to get clock from internal source
5	RESERVED	NONE	0h	Reserved
4	CPSW_CONTROL_RMII1_REF_CLK_OE_N	R/W	0h	RMII_REF_CLK IO Output enable control 1'b0: Output enable 1'b1: Output Disable
3	RESERVED	NONE	0h	Reserved
2:0	CPSW_CONTROL_PORT1_MODE_SEL	R/W	0h	Port 1 Interface 3'b000 = MII 3'b001 = RMII 3'b010 = RGMII 011 - 111 = Not Supported