SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

2.2.2.105 MSS_CTRL_MPU_PROT_INTR_ERRAGG0_STATUS_RAW Register

2.2.105.1 MSS_CTRL_MPU_PROT_INTR_ERRAGG0_STATUS_RAW Register (Offset = 4038h) [reset = 0h]

This register shows the Status of all MPU Protection Errors.

Table 2-211 Instance Table

Instance Name	Physical Address
MSS_CTRL	50D0 4038h

Figure 2-105 MSS_CTRL_MPU_PROT_INTR_ERRAGG0_STATUS_RAW Name Register

31	30	29	28	27	26	25	24
RESERVED
NONE
0h
23	22	21	20	19	18	17	16
RESERVED						MPU_PROT_INTR_ERRAGG0_STATUS_RAW_MPU_HSM_PROT_ERR0	MPU_PROT_INTR_ERRAGG0_STATUS_RAW_MPU_CR5B1_AHB_PROT_ERR0
NONE						R/W	R/W
0h						0h	0h
15	14	13	12	11	10	9	8
MPU_PROT_INTR_ERRAGG0_STATUS_RAW_MPU_CR5A1_AHB_PROT_ERR0	MPU_PROT_INTR_ERRAGG0_STATUS_RAW_MPU_CR5B0_AHB_PROT_ERR0	MPU_PROT_INTR_ERRAGG0_STATUS_RAW_MPU_CR5A0_AHB_PROT_ERR0	MPU_PROT_INTR_ERRAGG0_STATUS_RAW_MPU_SCRM2SCRP1_PROT_ERR0	MPU_PROT_INTR_ERRAGG0_STATUS_RAW_MPU_SCRM2SCRP0_PROT_ERR0	MPU_PROT_INTR_ERRAGG0_STATUS_RAW_MPU_QSPI_PROT_ERR0	MPU_PROT_INTR_ERRAGG0_STATUS_RAW_MPU_MBOX_PROT_ERR0	MPU_PROT_INTR_ERRAGG0_STATUS_RAW_MPU_DTHE_A_PROT_ERR0
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
0h	0h	0h	0h	0h	0h	0h	0h
7	6	5	4	3	2	1	0
MPU_PROT_INTR_ERRAGG0_STATUS_RAW_MPU_CR5B1_AXIS_PROT_ERR0	MPU_PROT_INTR_ERRAGG0_STATUS_RAW_MPU_CR5A1_AXIS_PROT_ERR0	MPU_PROT_INTR_ERRAGG0_STATUS_RAW_MPU_CR5B0_AXIS_PROT_ERR0	MPU_PROT_INTR_ERRAGG0_STATUS_RAW_MPU_CR5A0_AXIS_PROT_ERR0	MPU_PROT_INTR_ERRAGG0_STATUS_RAW_MPU_L2_BANK_D_PROT_ERR0	MPU_PROT_INTR_ERRAGG0_STATUS_RAW_MPU_L2_BANK_C_PROT_ERR0	MPU_PROT_INTR_ERRAGG0_STATUS_RAW_MPU_L2_BANK_B_PROT_ERR0	MPU_PROT_INTR_ERRAGG0_STATUS_RAW_MPU_L2_BANK_A_PROT_ERR0
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
0h	0h	0h	0h	0h	0h	0h	0h

Table 2-212 MSS_CTRL_MPU_PROT_INTR_ERRAGG0_STATUS_RAW Register Field Descriptions

Bit	Field	Type	Reset	Description
31:18	RESERVED	NONE	0h	Reserved
17	MPU_PROT_INTR_ERRAGG0_STATUS_RAW_MPU_HSM_PROT_ERR0	R/W	0h	Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK
16	MPU_PROT_INTR_ERRAGG0_STATUS_RAW_MPU_CR5B1_AHB_PROT_ERR0	R/W	0h	Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK
15	MPU_PROT_INTR_ERRAGG0_STATUS_RAW_MPU_CR5A1_AHB_PROT_ERR0	R/W	0h	Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK
14	MPU_PROT_INTR_ERRAGG0_STATUS_RAW_MPU_CR5B0_AHB_PROT_ERR0	R/W	0h	Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK
13	MPU_PROT_INTR_ERRAGG0_STATUS_RAW_MPU_CR5A0_AHB_PROT_ERR0	R/W	0h	Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK
12	MPU_PROT_INTR_ERRAGG0_STATUS_RAW_MPU_SCRM2SCRP1_PROT_ERR0	R/W	0h	Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK
11	MPU_PROT_INTR_ERRAGG0_STATUS_RAW_MPU_SCRM2SCRP0_PROT_ERR0	R/W	0h	Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK
10	MPU_PROT_INTR_ERRAGG0_STATUS_RAW_MPU_QSPI_PROT_ERR0	R/W	0h	Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK
9	MPU_PROT_INTR_ERRAGG0_STATUS_RAW_MPU_MBOX_PROT_ERR0	R/W	0h	Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK
8	MPU_PROT_INTR_ERRAGG0_STATUS_RAW_MPU_DTHE_A_PROT_ERR0	R/W	0h	Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK
7	MPU_PROT_INTR_ERRAGG0_STATUS_RAW_MPU_CR5B1_AXIS_PROT_ERR0	R/W	0h	Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK
6	MPU_PROT_INTR_ERRAGG0_STATUS_RAW_MPU_CR5A1_AXIS_PROT_ERR0	R/W	0h	Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK
5	MPU_PROT_INTR_ERRAGG0_STATUS_RAW_MPU_CR5B0_AXIS_PROT_ERR0	R/W	0h	Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK
4	MPU_PROT_INTR_ERRAGG0_STATUS_RAW_MPU_CR5A0_AXIS_PROT_ERR0	R/W	0h	Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK
3	MPU_PROT_INTR_ERRAGG0_STATUS_RAW_MPU_L2_BANK_D_PROT_ERR0	R/W	0h	Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK
2	MPU_PROT_INTR_ERRAGG0_STATUS_RAW_MPU_L2_BANK_C_PROT_ERR0	R/W	0h	Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK
1	MPU_PROT_INTR_ERRAGG0_STATUS_RAW_MPU_L2_BANK_B_PROT_ERR0	R/W	0h	Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK
0	MPU_PROT_INTR_ERRAGG0_STATUS_RAW_MPU_L2_BANK_A_PROT_ERR0	R/W	0h	Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK