SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

2.2.2.149 MSS_CTRL_MSS_TPCC_A_ERRAGG_STATUS_RAW Register

2.2.149.1 MSS_CTRL_MSS_TPCC_A_ERRAGG_STATUS_RAW Register (Offset = 18008h) [reset = 0h]

This register shows the Status of all Errors from TPCC0.

Table 2-299 Instance Table

Instance Name	Physical Address
MSS_CTRL	50D1 8008h

Figure 2-149 MSS_CTRL_MSS_TPCC_A_ERRAGG_STATUS_RAW Name Register

31	30	29	28	27	26	25	24
RESERVED					MSS_TPCC_A_ERRAGG_STATUS_RAW_TPTC_A1_READ_ACCESS_ERROR	MSS_TPCC_A_ERRAGG_STATUS_RAW_TPTC_A0_READ_ACCESS_ERROR	MSS_TPCC_A_ERRAGG_STATUS_RAW_TPCC_A_READ_ACCESS_ERROR
NONE					R/W	R/W	R/W
0h					0h	0h	0h
23	22	21	20	19	18	17	16
RESERVED					MSS_TPCC_A_ERRAGG_STATUS_RAW_TPTC_A1_WRITE_ACCESS_ERROR	MSS_TPCC_A_ERRAGG_STATUS_RAW_TPTC_A0_WRITE_ACCESS_ERROR	MSS_TPCC_A_ERRAGG_STATUS_RAW_TPCC_A_WRITE_ACCESS_ERROR
NONE					R/W	R/W	R/W
0h					0h	0h	0h
15	14	13	12	11	10	9	8
RESERVED
NONE
0h
7	6	5	4	3	2	1	0
RESERVED			MSS_TPCC_A_ERRAGG_STATUS_RAW_TPCC_A_PAR_ERR	MSS_TPCC_A_ERRAGG_STATUS_RAW_TPTC_A1_ERR	MSS_TPCC_A_ERRAGG_STATUS_RAW_TPTC_A0_ERR	MSS_TPCC_A_ERRAGG_STATUS_RAW_TPCC_A_MPINT	MSS_TPCC_A_ERRAGG_STATUS_RAW_TPCC_A_ERRINT
NONE			R/W	R/W	R/W	R/W	R/W
0h			0h	0h	0h	0h	0h

Table 2-300 MSS_CTRL_MSS_TPCC_A_ERRAGG_STATUS_RAW Register Field Descriptions

Bit	Field	Type	Reset	Description
31:27	RESERVED	NONE	0h	Reserved
26	MSS_TPCC_A_ERRAGG_STATUS_RAW_TPTC_A1_READ_ACCESS_ERROR	R/W	0h	Raw Status of Error from MSS_TPTC_A1. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_ERRAGG_MASK
25	MSS_TPCC_A_ERRAGG_STATUS_RAW_TPTC_A0_READ_ACCESS_ERROR	R/W	0h	Raw Status of Error from MSS_TPTC_A0. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_ERRAGG_MASK
24	MSS_TPCC_A_ERRAGG_STATUS_RAW_TPCC_A_READ_ACCESS_ERROR	R/W	0h	Raw Status of Error from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_ERRAGG_MASK
23:19	RESERVED	NONE	0h	Reserved
18	MSS_TPCC_A_ERRAGG_STATUS_RAW_TPTC_A1_WRITE_ACCESS_ERROR	R/W	0h	Raw Status of Error from MSS_TPTC_A1. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_ERRAGG_MASK
17	MSS_TPCC_A_ERRAGG_STATUS_RAW_TPTC_A0_WRITE_ACCESS_ERROR	R/W	0h	Raw Status of Error from MSS_TPTC_A0. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_ERRAGG_MASK
16	MSS_TPCC_A_ERRAGG_STATUS_RAW_TPCC_A_WRITE_ACCESS_ERROR	R/W	0h	Raw Status of Error from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_ERRAGG_MASK
15:5	RESERVED	NONE	0h	Reserved
4	MSS_TPCC_A_ERRAGG_STATUS_RAW_TPCC_A_PAR_ERR	R/W	0h	Raw Status of Error from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_ERRAGG_MASK
3	MSS_TPCC_A_ERRAGG_STATUS_RAW_TPTC_A1_ERR	R/W	0h	Raw Status of Error from MSS_TPTC_A1. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_ERRAGG_MASK
2	MSS_TPCC_A_ERRAGG_STATUS_RAW_TPTC_A0_ERR	R/W	0h	Raw Status of Error from MSS_TPTC_A0. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_ERRAGG_MASK
1	MSS_TPCC_A_ERRAGG_STATUS_RAW_TPCC_A_MPINT	R/W	0h	Raw Status of Error from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_ERRAGG_MASK
0	MSS_TPCC_A_ERRAGG_STATUS_RAW_TPCC_A_ERRINT	R/W	0h	Raw Status of Error from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_ERRAGG_MASK