SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

2.2.2.402 MSS_CTRL_MSS_MBOX_BUS_SAFETY_ERR Register

2.2.402.1 MSS_CTRL_MSS_MBOX_BUS_SAFETY_ERR Register (Offset = 186A8h) [reset = 0h]

This Register provides the Error Status of Bus Safety Comparator of MBOX SRAM Target Port.

Table 2-805 Instance Table

Instance Name	Physical Address
MSS_CTRL	50D1 86A8h

Figure 2-402 MSS_CTRL_MSS_MBOX_BUS_SAFETY_ERR Name Register

31	30	29	28	27	26	25	24
MSS_MBOX_BUS_SAFETY_ERR_DED
R
0h
23	22	21	20	19	18	17	16
MSS_MBOX_BUS_SAFETY_ERR_SEC
R
0h
15	14	13	12	11	10	9	8
MSS_MBOX_BUS_SAFETY_ERR_COMP_CHECK
R
0h
7	6	5	4	3	2	1	0
MSS_MBOX_BUS_SAFETY_ERR_COMP_ERR
R
0h

Table 2-806 MSS_CTRL_MSS_MBOX_BUS_SAFETY_ERR Register Field Descriptions

Bit	Field	Type	Reset	Description
31:24	MSS_MBOX_BUS_SAFETY_ERR_DED	R	0h	This flag signals detection of dual error in Data at this port.Flag is generted for 32 bit segment of Data Bus Bit 0 - 1'b1 indicates ded on [31:0] bit of Data bus Bit 1 - 1'b1 indicates ded on [63:32] bit of Data bus Bit [7:2] - Unused. Set to 1'b0
23:16	MSS_MBOX_BUS_SAFETY_ERR_SEC	R	0h	This flag signals detection of single error in Data at this port. Flag is generted for 32 bit segment of Data Bus Bit 0 - 1'b1 indicates sec on [31:0] bit of Data bus Bit 1 - 1'b1 indicates sec on [63:32] bit of Data bus Bit [7:2] - Unused. Set to 1'b0
15:8	MSS_MBOX_BUS_SAFETY_ERR_COMP_CHECK	R	0h	This is used to verify the proper functioning of fault Injection on all the buses.1'b1 indicates error in the corresponding Bus has been injected successfully. Bit 0 - This is a Bitwise AND of error compares of all command bus signals. Bit 1 - This is a Bitwise AND of error compares of all write bus signals. Bit 2 - This is a Bitwise AND of error compares of all write status bus signals. Bit 3 - This is a Bitwise AND of error compares of all read bus signals. Bits [7:4] are unused.
7:0	MSS_MBOX_BUS_SAFETY_ERR_COMP_ERR	R	0h	1'b1 indicates error in the corresponding Bus whenever a fault is detected at any bus signal Bit 0 - This is a Bitwise OR of error compares of all command bus signals. Bit 1 - This is a Bitwise OR of error compares of all write bus signals. Bit 2 - This is a Bitwise OR of error compares of all write status bus signals. Bit 3 - This is a Bitwise OR of error compares of all read bus signals. Bits [7:4] are unused.