SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Host Control 2 Register and Auto CMD Error Status Register
This register is used to indicate CMD12 response error of Auto CMD12 and CMD23 response error of Auto CMD23. The Host driver can determine what kind of Auto CMD12 / CMD23 errors occur by this register. Auto CMD23 errors are indicated in bit 04-01.This register is valid only when the Auto CMD Error is set.
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 4830 023Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PV_ENABLE | AI_ENABLE | RESERVED2 | |||||
| R/W | R/W | R | |||||
| 0h | 0h | 0h | |||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| SCLK_SEL | ET | DS_SEL | V1V8_SIGEN | UHSMS | |||
| R/W | R/W | R/W | R/W | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED1 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CNI | RESERVED | ACIE | ACEB | ACCE | ACTO | ACNE | |
| R | R | R | R | R | R | R | |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | PV_ENABLE | R/W | 0h | Preset Value Enable Host Controller Version 3.00 supports this bit. As the operating SDCLK frequency and I/O driver strength depend on the Host System implementation, it is difficult to determine these parameters in the Standard Host Driver. When Preset Value Enable is set, automatic SDCLK frequency generation and driver strength selection is performed without considering system specific conditions. This bit enables the functions defined in the Preset Value registers. If this bit is set to 0, SDCLK Frequency Select, Clock Generator Select in the Clock Control register and Driver Strength Select in Host Control 2 register are set by Host Driver. If this bit is set to 1, SDCLK Frequency Select, Clock Generator Select in the Clock Control register and Driver Strength Select in Host Control 2 register are set by Host Controller as specified in the Preset Value registers. 1 Automatic Selection by Preset Value are
Enabled.
0 SDCLK and Driver Strength are controlled by
Host Driver. |
| 30 | AI_ENABLE | R/W | 0h | Asynchronous Interrupt Enable This bit can be set to 1 if a card supports asynchronous interrupts and Asynchronous Interrupt Support is set to 1 in the Capabilities register. Asynchronous interrupt is effective when DAT[1] interrupt is used in 4-bit SD mode [and zero is set to Interrupt Pin Select in the Shared Bus Control register]. If this bit is set to 1, the Host Driver can stop the SDCLK during asynchronous interrupt period to save power. During this period, the Host Controller continues to deliver the Card Interrupt to the host when it is asserted by the Card. 1 Enabled 0 Disabled |
| 29:24 | RESERVED2 | R | 0h | |
| 23 | SCLK_SEL | R/W | 0h | Sampling Clock Select Host Controller uses this bit to select sampling clock to receive CMD and DAT. This bit is set by tuning procedure and valid after the completion of tuning [when Execute Tuning is cleared]. Setting 1 means that tuning is completed successfully and setting 0 means that tuning is failed. Writing 1 to this bit is meaningless and ignored. A tuning circuit is reset by Writing to 0. This bit can be cleared with setting Execute Tuning. Once the tuning circuit is reset, it will take time to complete tuning sequence. Therefore, Host Driver should keep this bit to 1 to perform re-tuning sequence to compete re-tuning sequence in a short time. Change of this bit is not allowed while the Host Controller is receiving response or a read data block. 1 Tuned clock is used to sample data 0 Fixed clock is used to sample data |
| 22 | ET | R/W | 0h | Execute Tuning This bit is set to 1 to start tuning procedure and automatically cleared when tuning procedure is completed. The result of tuning is indicated to Sampling Clock Select. Tuning procedure is aborted by Writing 0. This is Read-Write with automatic clear register 1 Execute Tuning 0 Not Tuned or Tuning Completed |
| 21:20 | DS_SEL | R/W | 0h | Driver Strength Select Host Controller output driver in 1.8V signaling is selected by this bit. In 3.3V signaling, this field is not effective. This field can be set depends on Driver Type A, C and D support bits in the Capabilities register. This bit depends on setting of Preset Value Enable. If Preset Value Enable = 0, this field is set by Host Driver. If Preset Value Enable = 1, this field is automatically set by a value specified in the one of Preset Value registers. 3 Driver Type D is selected 2 Driver Type C is selected 1 Driver Type A is selected 0 Driver Type B is selected (Default) |
| 19 | V1V8_SIGEN | R/W | 0h | 1.8V Signaling Enable This bit controls voltage regulator for I/O cell. 3.3V is supplied to the card regardless of signaling voltage. Setting this bit from 0 to 1 starts changing signal voltage from 3.3V to 1.8V. 1.8V regulator output shall be stable within 5ms. Host Controller clears this bit if switching to 1.8V signaling fails. Clearing this bit from 1 to 0 starts changing signal voltage from 1.8V to 3.3V. 3.3V regulator output shall be stable within 5ms. Host Driver can set this bit to 1 when Host Controller supports 1.8V signaling [One of support bits is set to 1:SDR50, SDR104 or DDR50 in the Capabilities register] and the card or device supports UHS-I [S18A=1. Refer to Bus Signal Voltage Switch Sequence in the Physical Layer Specification Version 3.0x]. 1 1.8V Signaling 0 3.3V Signaling |
| 18:16 | UHSMS | R/W | 0h | UHS Mode Select This field is used to select one of UHS-I modes and effective when 1.8V Signaling Enable is set to 1. If Preset Value Enable in the Host Control 2 register is set to 1, Host Controller sets SDCLK Frequency Select, Clock Generator Select in the Clock Control register and Driver Strength Select according to Preset Value registers. In this case, one of preset value registers is selected by this field. Host Driver needs to reset SD Clock Enable before changing this field to avoid generating clock glitch. After setting this field, Host Driver sets SD Clock Enable again. When SDR50, SDR104 or DDR50 is selected for SDIO card, interrupt detection at the block gap shall not be used. Read Wait timing is changed for these modes. Refer to the SDIO Specification Version 3.00 for more detail. 7 Reserved 6 Reserved 5 Reserved 4 DDR50 3 SDR104 2 SDR50 1 SDR25 0 SDR12 |
| 15:8 | RESERVED1 | R | 0h | |
| 7 | CNI | R | 0h | Command Not Issued By Auto CMD12 Error Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 Error [D04-D01] in this register. This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. 1 Command not issued 0 Not error |
| 6:5 | RESERVED | R | 0h | |
| 4 | ACIE | R | 0h | Auto CMD Index Error This bit is set if the Command Index error occurs in response to a command. 1 Error 0 No error |
| 3 | ACEB | R | 0h | Auto CMD End Bit Error This bit is set when detecting that the end bit of command response is 0. 1 End bit Error Generated 0 No error |
| 2 | ACCE | R | 0h | Auto CMD CRC Error This bit is set when detecting a CRC error in the command response. 1 CRC Error Generated 0 No error |
| 1 | ACTO | R | 0h | Auto CMD Timeout Error This bit is set if no response is returned within 64 SDCLK cycles from the end bit of command. If this bit is set to1, the other error status bits [D04-D02] are meaningless. 1 Auto CMD Time Out 0 No error |
| 0 | ACNE | R | 0h | Auto CMD12 Not Executed If memory multiple block data transfer is not started due to command error, this bit is not set because it is not necessary to issue Auto CMD12. Setting this bit to 1 means the Host Controller cannot issue Auto CMD12 to stop memory multiple block data transfer due to some error. If this bit is set to 1, other error status bits [D04-D01] are meaningless. This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. 1 Auto CMD12 Not Executed 0 Auto CMD12 Executed |