SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.15.2.28 MMC_FE Register

15.2.28.1 MMC_FE Register (Offset = 250h) [reset = 0h]

Force Event Register for Auto CMD Error Status and Error Interrupt status

The Force Event Register is not a physically implemented register. Rather, it is an address at which the Auto CMD Error Status Register can be written.
Writing 1 : set each bit of the Auto CMD Error Status Register
Writing 0 : no effect

Rather, it is an address at which the Error Interrupt Status register can be written. The effect of a write to this address will be reflected in the Error Interrupt Status Register if the corresponding bit of the Error Interrupt Status Enable Register is set.
Writing 1 : set each bit of the Error Interrupt Status Register
Writing 0 : no effect

Note: By setting this register, the Error Interrupt can be set in the Error Interrupt Status register. In order to generate interrupt signal, both the Error Interrupt Status Enable and Error Interrupt Signal Enable shall be set.

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Table 5-1818 Instance Table

Instance Name	Physical Address
MMCSD0	4830 0250h

Figure 5-897 MMC_FE Name Register

31	30	29	28	27	26	25	24
RESERVED3		FE_BADA	FE_CERR	RESERVED2		FE_ADMAE	FE_ACE
		W	W			W	W
0h		0h	0h	0h		0h	0h
23	22	21	20	19	18	17	16
FE_CLE	FE_DEB	FE_DCRC	FE_DTO	FE_CIE	FE_CEB	FE_CCRC	FE_CTO
	W	W	W	W	W	W	W
0h	0h	0h	0h	0h	0h	0h	0h
15	14	13	12	11	10	9	8
RESERVED1

0h
7	6	5	4	3	2	1	0
FE_CNI	RESERVED		FE_ACIE	FE_ACEB	FE_ACCE	FE_ACTO	FE_ACNE
W			W	W	W	W	W
0h	0h		0h	0h	0h	0h	0h

Table 5-1819 MMC_FE Register Field Descriptions

Bit	Field	Type	Reset	Description
31:30	RESERVED3		0h
29	FE_BADA	W	0h	Force Event Bad access to data space. 1 Interrupt Forced 0 No effect, No Interrupt.
28	FE_CERR	W	0h	Force Event Card error. 1 Interrupt Forced 0 No effect, No Interrupt.
27:26	RESERVED2		0h
25	FE_ADMAE	W	0h	Force Event ADMA Error. 1 Interrupt Forced 0 No effect, No Interrupt.
24	FE_ACE	W	0h	Force Event for Auto CMD Error 1 Interrupt Forced 0 No effect, No Interrupt.
23	FE_CLE		0h	Reserved. Current limit error is not supported. These bits are initialized to zero, and writes to them are ignored.
22	FE_DEB	W	0h	Force Event Data End Bit error. 1 Interrupt Forced 0 No effect, No Interrupt.
21	FE_DCRC	W	0h	Force Event Data CRC Error. 1 Interrupt Forced 0 No effect, No Interrupt.
20	FE_DTO	W	0h	Force Event Data Timeout Error. 1 Interrupt Forced 0 No effect, No Interrupt.
19	FE_CIE	W	0h	Force Event Command Index Error. 1 Interrupt Forced 0 No effect, No Interrupt.
18	FE_CEB	W	0h	Force Event Command End Bit Error. 1 Interrupt Forced 0 No effect, No Interrupt.
17	FE_CCRC	W	0h	Force Event Command CRC Error. 1 Interrupt Forced 0 No effect, No Interrupt.
16	FE_CTO	W	0h	Command Timeout Error This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command. For commands that reply within 5 clock cycles - the timeout is still detected at 64 clock cycles. 1 Status is cleared 0 Status bit unchanged
15:8	RESERVED1		0h
7	FE_CNI	W	0h	Force Event Command not issue by Auto CMD12 error 1 Interrupt Forced 0 No effect, No Interrupt.
6:5	RESERVED		0h
4	FE_ACIE	W	0h	Force Event for Auto CMD Index Error 1 Interrupt Forced 0 No effect, No Interrupt.
3	FE_ACEB	W	0h	Force Event Auto CMD End Bit Error 1 Interrupt Forced 0 No effect, No Interrupt.
2	FE_ACCE	W	0h	Force Event Auto CMD CRC Error 1 Interrupt Forced 0 No effect, No Interrupt.
1	FE_ACTO	W	0h	Force Event Auto CMD Timeout Error 1 Interrupt Forced 0 No effect, No Interrupt.
0	FE_ACNE	W	0h	Force Event Auto CMD12 Not Executed 1 Interrupt Forced 0 No effect, No Interrupt.