SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Versions Register
This register contains the hard coded RTL vendor revision number, the version number of SD specification compliancy and a slot status bit.
MMCHS_REV[31:16] = Host controller version
MMCHS_REV[15:0] = Slot Interrupt Status.
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Instance Name | Physical Address |
---|---|
MMCSD0 | 4830 02FCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
VREV | |||||||
R | |||||||
31h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SREV | |||||||
R | |||||||
1h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SIS | ||||||
R | R | ||||||
0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:24 | VREV | R | 31h | Vendor Version Number: IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 1.0 0x21 for 2.1 |
23:16 | SREV | R | 1h | Specification Version Number This status indicates the Host Controller Spec. Version. The upper and lower 4-bits indicate the version. 3 Reserved 2 SD Host Specification Version 3.00. 1 SD Host Specification Version 2.00 - Including the feature of the ADMA and Test Register. 0 SD Host Specification Version 1.00. |
15:1 | RESERVED | R | 0h | |
0 | SIS | R | 0h | Slot Interrupt Status This status bit indicates the inverted state of interrupt signal for the module. By a power on reset or by setting a software reset for all [MMCSD_HCTL[SRA]], the interrupt signal shall be de-asserted and this status shall read 0. |