This technical user’s guide describes the hardware architecture of the AM62x-Low Power SK EVM, a low cost starter kit built around the AM62x System-on-Chip (SoC). The AM62x processor comprises of a quad-core 64-bit Arm®-Cortex® A53 microprocessor, single-core Arm Cortex-R5F MCU and an Arm Cortex-M4F MCU.
The SK EVM allows the user to experience a great dual display feature through HDMI (over DPI) and LVDS, up to 2K resolution, as well as industrial communication solutions using serial, Ethernet, USB and other interfaces. Its powerful Arm performance, up to quad-core Cortex-A53 at 1.4GHz, with rich interfaces, offers good control and communication capabilities for a wide ranges of automotive applications such as automotive HMI and driver monitoring system, as well as industrial applications such as PLC, automation control, monitor/supervisor system. In addition, the SK EVM can communicate with other processors or systems, and act as a communication gateway. In addition, the SK EVM can directly operate as a standard remote I/O system or simple sensor connected to an industrial communication network. The embedded emulation logic allows for emulation and debugging using standard development tools such as Code Composer Studio™ from TI.
OPN | PCB Revision | Assembly Variant | Revision and Assembly Variant Description |
---|---|---|---|
SK-AM62-LP | PROC124E1 | N/A | First prototype, early release revision of the AM62X Low-Power SK EVM. Implements the Sitara AM62X MPU with a PMIC power solution. |
SK-AM62-LP | PROC124E2 | N/A | Second prototype, early release revision of the AM62X Low-Power SK EVM. Implements a number of changes and bug fixes. |
SK-AM62-LP | PROC124E2 | PROC124E2A | Few components updated in assembly |
Components installed on the product are sensitive to Electric Static Discharge (ESD). It is recommended this product be used in an ESD controlled enviorment. This may include a temperature and/or humidty controlled enviorment to limit the buildup of ESD. It is also recommended to use ESD protection such as wrist straps and ESD mats when interfacing with the product.
The product is used in the basic electromagnetic enviorment as in laboratory conditions, and the applied standard is as per EN IEC 61326-1:2021.
All trademarks are the property of their respective owners.
The AM62x-Low Power SK EVM is a high performance, standalone development platform that enables users to evaluate and develop industrial applications for the Texas Instrument’s AM62x System-on-Chip (SoC).
The following sections discuss the SK EVM’s key features.
AM62x-Low Power SK EVM utilizes an array of DC-DC converters to supply the various memories, clocks, SoC and other components on the board with the necessary voltage and the power required.
The figure below shows the various discrete regulators and LDOs used to generate power rails and the current consumption of each peripheral on AM62x-Low Power SK EVM board.
The following sections describe the power distribution network topology that supplies the SK EVM board, supporting components and reference voltages.
The AM62x-Low Power SK EVM board includes a power solution based on a PMIC as well as discrete power supply components. The initial stage of the power supply will be VBUS voltage from either of the two USB Type C connectors J13 and J15. USB Type-C Dual PD controller of Mfr. Part# TPS65988DHRSHR is used for negotiation of the required power to the system.
Buck-Boost controller TPS630702RNMR and Buck converter LM61460-Q1 are used for the generation of 5V and 3.3V respectively and the input to the regulators is the PD output. These 3.3V and 5V are the primary voltages for the AM62x-Low Power SK EVM Board power resources. The 3.3V supply generated from the Buck regulator LM61460-Q1 is the input supply to the Various SOC regulators and LDOs. The 5V supply generated from the Buck Boost regulator TPS630702RNMR is used for powering the onboard peripherals. Discrete regulators and LDOs used on board are:
Additionally, GPIO from the test automation header is also connected to the TPS630702RNMR Enable pin to control ON/OFF of the SKEVM via the test automation board. It only disables the VCC_5V0 output of TPS630702RNMR from which all other power supplies are derived. SoC has different IO groups.
The power sequencing of AM62x-Low Power EVM is given below.
The core voltage of the AM62x 17x17 SoC can be 0.75 V or 0.85 V based on the PMIC configuration and on the power optimization requirement. By default, the PMIC configured as VDD_CORE = 0.75V, it can be changed to 0.85V by changing the PMIC configuration register. Current monitors are provided on all the SoC power rails.
The SoC has different IO groups. Each IO group is powered by specific power supplies as shown in the table below.
Sl.No | Power Supply | SoC Supply Rails | IO Power Group | Voltage |
---|---|---|---|---|
1 | VDD_CORE | VDDA_CORE_USB | 0.75 | |
VDDA_CORE_CSI | ||||
VDD_CANUART | CANUART | |||
VDD_CORE | CORE | |||
2 | VDDR_CORE | VDDR_CORE | CORE | 0.85 |
3 | VDDA_1V8 | VDDA_1V8_CSIRX. | CSI | 1.8 |
VDDA_1V8_USB | USB | |||
VDDA_1V8_MCU | ||||
VDDA_1V8_OLDI | OLDI | |||
VDDA_1V8_OSCO | OSCO | |||
VDDA_PLL0, VDDA_PLL1,VDDA_PLL2 | ||||
4 | VDD_LPDDR4 | VDDS_DDR | DDR0 | 1.1 |
VDDS_DDR_C | ||||
5 | VPP_1V8 | VPP_1V8 | 1.8 | |
6 | SoC_VDDSHV5_SDIO | VDDSHV5 | MMC1 | 3.3 |
7 | SOC_DVDD1V8 | VDDSHV0 | General | 3.3 |
VDDSHV1 | OSPI | 1.8 | ||
VDDSHV4 | MMC0 | |||
VDDSHV6 | MMC2 | |||
VMON_1P8_SOC | ||||
8 | SOC_DVDD3V3 | VDDSHV0 | General | 3.3 |
VDDSHV2 | RGMII | |||
VDDSHV3 | GPMC | |||
VDDSHV_MCU | MCU General | |||
VMON_3P3_SOC | ||||
VDDA_3P3_USB | USB | |||
INA231 power monitor devices are used to monitor current and voltage of various power rails of AM62x 17x17 SoC. The INA231 interfaces to the AM62x 17x17 SoC through I2C interface (SoC_I2C1). Four terminal, high precision shunt resistors are provided to measure load current.
Source | Supply net | DeviceAddress | Valueof the Shunt Connected to the Supply Rail |
VCC_CORE | VDD_CORE | 0x40 | 10mΩ± 1% |
VCC_0V85 | VDDR_CORE | 0x41 | 10mΩ± 1% |
VCC_3V3_SYS | SoC_DVDD3V3 | 0x4C | 10mΩ± 1% |
VCC_1V8 | SoC_DVDD1V8 | 0x45 | 10mΩ± 1% |
VDDA1V8 | VDDA_1V8 | 0x4E | 10mΩ± 1% |
VCC1V1 | VDD_LPDDR4 | 0x46 | 10mΩ± 1% |
AM62x-Low Power SK EVM has two 8 - position DIP Switch to set the SoC Boot mode and related parameters.
The boot mode for the AM62x-Low power SK EVM board is defined by two banks of switches SW3 and SW4 or by the I2C buffer connected to the Test automation connector. This allows for AM62x SoC Boot mode control by either the user (DIP Switch Control) or by the Test Automation connector.
All the bits of switch (SW3 & SW4) have week pull down resistor and a strong pull up resistor as shown in below picture. Note that OFF setting provides a low logic level (‘0’) and an ON setting provides a high logic level (‘1’).
The boot mode pins of the SoC have associated alternate functions during normal operation. Hence isolation isprovided using Buffer IC’s to cater for alternate pin functionality. The output of the buffer is connected to the bootmode pins on the AM62x Low Power SK EVM. The output is enabled when the bootmode is needed during a reset cycle.
The input to the buffer is connected to the DIP switch circuit and to the output of an I2C buffer set by the test automatio ncircuit. If the test automation circuit is going to control the bootmode, all the switches will manually be set to the OFF position. The bootmode buffer should be powered by an always ON power supply to ensure that the bootmode remains present even if the SoC power is cycled.
Switch SW1 and SW2 bits [15:0] are used to set the SoC Boot mode.
The switch map to the boot mode functions is provided in the tables below.
Bit15 | Bit14 | Bit13 | Bit12 | Bit11 | Bit10 | Bit9 | Bit8 | Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Reserved | Backup Boot Mode Configuration | Backup Boot Mode | Primary Boot Mode Configuration | Primary Boot Mode | PLL Configuration |
BOOT-MODE[0:2] – Denote system clock frequency for PLL configuration. By default this bits are set for 25MHz.
SW3.3 | SW3.2 | SW3.1 | PLL REF CLK (MHz) |
---|---|---|---|
OFF | OFF | OFF | RSVD |
OFF | OFF | ON | RSVD |
OFF | ON | OFF | 24 |
OFF | ON | ON | 25 |
ON | OFF | OFF | 26 |
ON | OFF | ON | RSVD |
ON | ON | OFF | RSVD |
ON | ON | ON | RSVD |
BOOT-MODE [3:6] – This provides primary boot mode configuration to select the requested boot mode after POR, that is, the peripheral/memory to boot from primary boot device selection details.
SW3.7 | SW3.6 | SW3.5 | SW3.4 | Primary Boot Device Selected |
---|---|---|---|---|
OFF | OFF | OFF | OFF | Serial NAND |
OFF | OFF | OFF | ON | OSPI |
OFF | OFF | ON | OFF | QSPI |
OFF | OFF | ON | ON | SPI |
OFF | ON | OFF | OFF | Ethernet RGMII1 |
OFF | ON | OFF | ON | Ethernet RMII1 |
OFF | ON | ON | OFF | I2C |
OFF | ON | ON | ON | UART |
ON | OFF | OFF | OFF | MMC/SD card |
ON | OFF | OFF | ON | eMMC |
ON | OFF | ON | OFF | USB0 |
ON | OFF | ON | ON | GPMC NAND |
ON | ON | OFF | OFF | GPMC NOR |
ON | ON | OFF | ON | Rsvd |
ON | ON | ON | OFF | xSPI |
ON | ON | ON | ON | No boot/Dev Boot |
• BOOT-MODE [10:12] – Select the backup boot mode, used when the primary boot mode is not available.
SW4.5 | SW4.4 | SW4.3 | Backup Boot Device Selected |
---|---|---|---|
OFF | OFF | OFF | None(No backup mode) |
OFF | OFF | ON | USB |
OFF | ON | OFF | Reserved |
OFF | ON | ON | UART |
ON | OFF | OFF | Ethernet |
ON | OFF | ON | MMC/SD |
ON | ON | OFF | SPI |
ON | ON | ON | I2C |
BOOT-MODE [9:7] – These pins provide optional settings and are used in conjunction with the primary boot device selected.
SW4.2 | SW4.1 | SW3.8 | Boot Device |
---|---|---|---|
Reserved | Read Mode 2 | Read Mode 1 | Serial NAND |
Reserved | Iclk | Csel | QSPI |
Speed | Iclk | Csel | OSPI |
Reserved | Mode | Csel | SPI |
Clkout | 0 | Link stat | Ethernet RGMII |
Clkout | Clk src | 0 | Ethernet RMII |
Bus Reset | Reserved | Addr | I2C |
Reserved | Reserved | Reserved | UART |
Port | Reserved | Fs/raw | MMC/ SD card |
Reserved | Reserved | Reserved | eMMC |
Core Volt | Mode | Lane swap | USB0 |
Reserved | Reserved | Reserved | GPMC NAND |
Reserved | Reserved | Reserved | GPMC NOR |
Reserved | Reserved | Reserved | Reserved |
SFDP | Read Cmd | Mode | xSPI |
Reserved | ARM/Thumb | No/Dev | No boot/Dev Boot |
BOOT-MODE[13] – These pins provide optional settings and are used in conjunction with the backup boot device devices. Switch SW2.6 when ON sets 1 and sets 0 if OFF, see the device-specific TRM.
BOOT-MODE [14:15] – Reserved. Provides backup boot media configuration options.
SW4.6 | Boot Device |
---|---|
Reserved | None |
Mode | USB |
Reserved | Reserved |
Reserved | UART |
IF | Ethernet |
Port | MMC/SD |
Reserved | SPI |
Reserved | I2C |
The AM62x-Low Power SK EVM contains two LEDs for user defined functions.
The table below indicates the User test LEDs and the associated GPIOs used to control it.
Sl # | LED | GPIO used | SCH Net Names |
1 | LD3 | GPIO1_49 | SOC_GPIO1_49 |
2 | LD7 | U70.24(P27) | IO_EXP_TEST_LED |
The AM62x-Low Power SK EVM features three expansion headers: the 40 pin User expansion connector, 20 pin PRU Header and the 28 pin MCU Header.
The AM62x-Low Power SK EVM supports RPi expansion interface using a 40-pin User expansion connector Mfr. Part# PEC20DAAN. Four mounting holes must be oriented with the connector to allow for connection of these boards.
The following interfaces and IOs are included on to the 40 pin User Expansion connector.
Each of the power supplies 5V and 3.3V are current limited to 155mA and 500mA respectively. This is achieved by using two individual load switches TPS22902YFPR and TPS22946YZPR. The Enable signals for the load switches is driven via I2C based GPIO Port expander.
Pin No. | SoC Ball | Net name | Comments |
---|---|---|---|
1 | - | VCC3V3_EXP | |
2 | - | VCC5V0_EXP | |
3 | H19 | EXP_I2C2_SDA | I2C SW |
4 | - | VCC5V0_EXP | |
5 | H18 | EXP_I2C2_SCL | I2C SW |
6 | - | DGND | |
7 | C14 | EXP_CLKOUT0 | |
8 | A15 | EXP_UART5_TXD | |
9 | - | DGND | |
10 | B13 | EXP_UART5_RXD | |
11 | C17 | EXP_SPI2_CS1 | |
12 | D15 | EXP_SPI2_CS0/EHRPWM0_A | MUX |
13 | H17 | EXP_GPIO0_42 | |
14 | - | DGND | |
15 | - | EXP_GPIO0_22 | |
16 | P17 | EXP_GPIO0_38 | |
17 | - | VCC3V3_EXP | |
18 | J20 | EXP_GPIO0_39 | |
19 | C12 | EXP_SPI0_D0 | |
20 | - | DGND | |
21 | A14 | EXP_SPI0_D1 | |
22 | E18 | EXP_GPIO0_14 | |
23 | D12 | EXP_SPI0_CLK | |
24 | C11 | EXP_SPI0_CS0 | |
25 | - | DGND | |
26 | D13 | EXP_SPI0_CS1 | |
27 | D14 | SoC_I2C0_SDA | |
28 | E12 | SoC_I2C0_SCL | |
29 | K18 | EXP_GPIO0_36 | |
30 | K20 | EXP_GPIO0_32 | |
31 | K21 | EXP_GPIO0_33 | |
32 | J19 | EXP_GPIO0_40/ PR0_ECAP0_IN_APWM_OUT | |
33 | D18 | EXP_EHRPWM1_B | |
34 | - | DGND | |
35 | B17 | EXP_SPI2_D1/ ECAP2_IN_APWM_OUT | MUX |
36 | A18 | EXP_SPI2_CS2 | |
37 | J18 | EXP_GPIO0_41 | |
38 | B18 | EXP_SPI2_D0 | MUX |
39 | - | EXP_HAT_DETECT | |
40 | D16 | EXP_SPI2_CLK | MUX |
The AM62x-Low Power SK EVM has a 14x2 standard 0.1 spaced MCU connector which includes signals connected to the MCU Domain of SoC. 13 Signals include MCU_I2C0, MCU_UART0 (with flow control), MCU_SPI0 and MCU_MCAN0 signals are connected to the MCU Header. Additional control signals provided on the Header include CONN_MCU_RESETz, CONN_MCU_PORz, MCU_RESETSTATz, MCU_SAFETY_ERRORn, 3.3V IO and GND. MCU_UART0 signals from AM62x SoC are connected to both MCU Header and FT4232 Bridge through MUX Mfr Part # SN74CB3Q3257PWR. The MCU Header does not include the Board ID memory interface. Allowed current limit is 100mA on 3.3V rail.
Pin No. | SoCBall No. | Netname |
1 | - | VCC_3V3_SYS |
2 | - | DGND |
3 | - | DGND |
4 | D8 | MCU_SPI0_D1 |
5 | - | CAN_FD_WKUP_HDR_INH |
6 | E8 | MCU_SPI0_D0 |
7 | - | DGND |
8 | C8 | MCU_SPI0_CS1 |
9 | - | DGND |
10 | D5 | MCU_GPIO0_15 |
11 | D6 | MCU_GPIO0_16 |
12 | B8 | MCU_UART0_CTS_CONN |
13 | A8 | MCU_UART0_RXD_CONN |
14 | - | DGND |
15 | - | DGND |
16 | C5 | MCU_MCAN0_TX |
17 | D7 | MCU_UART0_RTS_CONN |
18 | B7 | MCU_SPI0_CLK |
19 | B6 | MCU_UART0_TXD_CONN |
20 | - | DGND |
21 | A10 | MCU_I2C0_SDA |
22 | C4 | MCU_MCAN0_RX |
23 | A12 | MCU_RESETSTATz |
24 | B9 | MCU_I2C0_SCL |
25 | - | CONN_MCU_RESETz |
26 | - | MCU_SAFETY_ERRORz_3V3 |
27 | - | DGND |
28 | - | CONN_MCU_PORz |
The AM62x-Low Power SK EVM has a 20 pin PRU Header which offers a low speed connection to the PRG0 Interface using a connector Mfr Part # PREC010DAAN-RC. The connector features PR0_PRU0_GPO [0: 7], SoC_I2C0, +3.3V PRU_ICSSG signals from PRG0 Port (PRG0_PRU0) are connected to a 10x2 standard 0.1” spaced Receptacle PWR and Ground reference. INTn signal from PRU Header is wired along with the CPSW PHY interrupts and connected to the EXTINTn pin of the SoC.
The 3.3V supply is current limited to 500mA. This is achieved by using load switch TPS22902YFPR. Enable for the load switch is controlled by IO expander. Signals routed from the PRU Connector are listed in the table below.
Pin No. | SoC Ball No. | Net name |
1 | - | VCC3V3_PRU |
2 | - | DGND |
3 | - | PRU_DETECT |
4 | - | PRU_RESETz |
5 | B16 | PRU_INTn |
6 | E12 | SoC_I2C0_SCL |
7 | J17 | PR0_PRU0_GPO11 |
8 | D14 | SoC_I2C0_SDA |
9 | P21 | PR0_PRU0_GPO12 |
10 | - | NC |
11 | K17 | PR0_PRU0_GPO14 |
12 | - | NC |
13 | K19 | PR0_PRU0_GPO0 |
14 | L19 | PR0_PRU0_GPO1 |
15 | L20 | PR0_PRU0_GPO2 |
16 | L21 | PR0_PRU0_GPO3 |
17 | M21 | PR0_PRU0_GPO4 |
18 | L17 | PR0_PRU0_GPO5 |
19 | L18 | PR0_PRU0_GPO6 |
20 | M20 | PR0_PRU0_GPO7 |
AM62x-Low Power SK EVM supports two interrupts for providing Reset input and User Interrupt to the processor. The interrupts are push buttons placed on the Top side of the Board and are listed in the table below.
Sl # | Push Buttons | Signal | Function |
1 | SW5 | SoC_WARM_RESETZ | Maindomain Warm Reset input |
2 | SW6 | GPIO_MCU | Generatesinterrupt on MCU_GPIO0_15 |
There are three I2C interfaces used in AM62x-Low Power SK EVM board.
I2C Port | Device/Function | Part# | I2C Address |
SoC_I2C0 | Board ID EEPROM | M24512-DFMC6TG | 0x51 |
SoC_I2C0 | User Expansion Connector | <connector interface> | |
SoC_I2C0 | USB PD Controller | TPS65988DHRSHR | 0x38, 0x3F |
SoC_I2C0 | PRU Header | <connector interface> | |
SoC_I2C0 | OLDI Display Touch Interface | <connector interface> | |
SoC_I2C1 | PMIC | TPS65219 | 0x30 |
SoC_I2C1 | Test Automation Header | <connector interface> | |
SoC_I2C1 | Current Monitors | INA231AIYFDR |
0x40, 0x41, 0x4C, 0x45, 0x4E & 0x46 |
SoC_I2C1 | Temperature Sensors | TMP100NA/3K | 0x48, 0x49 |
SoC_I2C1 | Audio Codec | TLV320AIC3106IRGZT | 0x1B |
SoC_I2C1 | HDMI Transmitter | SiI9022ACNU | 0x3B, 0x3F, 0x62 |
SoC_I2C1 | GPIO Port Expander | TCA6424ARGJR | 0x22, 0x23 |
SoC_I2C2 | CSI Camera Connector | <connector interface> | |
SoC_I2C2 | User Expansion Connector | <connector interface> | |
MCU_I2C0 | MCU Header | <connector interface> | |
Others | |||
BOOTMODE_I2C | I2C Bootmode Buffer | TCA6424ARGJR | 0x22 |
BOOTMODE_I2C | Test Automation Header | <connector interface> |