SPRUJ51 june   2023

 

  1.   1
  2. 1Abstract
  3. 2EVM Revisions and Assembly Variants
    1. 2.1 Inside the Box
    2. 2.2 EMC, EMI and ESD Compliance
  4.   Trademarks
  5. 3System Description
    1. 3.1 Key Features
      1. 3.1.1 Processor
      2. 3.1.2 Power Supply
      3. 3.1.3 Memory
      4. 3.1.4 JTAG Emulator
      5. 3.1.5 Supported Interfaces and Peripherals
      6. 3.1.6 Expansion Connectors Headers to Support Application Specific Add On Boards
    2. 3.2 Functional Block Diagram
    3. 3.3 AM62x-Low Power SK EVM Interface Mapping
    4. 3.4 Power ON OFF Procedures
      1. 3.4.1 Power-On Procedure
      2. 3.4.2 Power-Off Procedure
      3. 3.4.3 Power Test Points
    5. 3.5 Peripheral and Major Component Description
      1. 3.5.1  Clocking
      2. 3.5.2  Reset
      3. 3.5.3  OLDI Display Interface
      4. 3.5.4  CSI Interface
      5. 3.5.5  Audio Codec Interface
      6. 3.5.6  HDMI Display Interface
      7. 3.5.7  JTAG Interface
      8. 3.5.8  Test Automation Header
      9. 3.5.9  UART Interface
      10. 3.5.10 USB Interface
        1. 3.5.10.1 USB 2.0 Type A Interface
        2. 3.5.10.2 USB 2.0 Type C Interface
      11. 3.5.11 Memory Interfaces
        1. 3.5.11.1 LPDDR4 Interface
        2. 3.5.11.2 OSPI Interface
        3. 3.5.11.3 MMC Interfaces
          1. 3.5.11.3.1 MMC0 - eMMC Interface
          2. 3.5.11.3.2 MMC1 - Micro SD Interface
          3. 3.5.11.3.3 MMC2 - M2 Key E Interface
        4. 3.5.11.4 EEPROM
      12. 3.5.12 Ethernet Interface
        1. 3.5.12.1 CPSW Ethernet PHY1 Default Configuration
        2. 3.5.12.2 CPSW Ethernet PHY2 Default Configuration
      13. 3.5.13 GPIO Port Expander
      14. 3.5.14 GPIO Mapping
      15. 3.5.15 Power
        1. 3.5.15.1 Power Requirements
        2. 3.5.15.2 Power Input
        3. 3.5.15.3 Power Supply
        4. 3.5.15.4 Power Sequencing
        5. 3.5.15.5 AM62x 17x17 SoC Power
        6. 3.5.15.6 Current Monitoring
      16. 3.5.16 AM62x-Low Power SK EVM User Setup and Configuration
        1. 3.5.16.1 EVM DIP Switches
        2. 3.5.16.2 Boot Modes
        3. 3.5.16.3 User Test LEDs
      17. 3.5.17 Expansion Headers
        1. 3.5.17.1 User Expansion Connector
        2. 3.5.17.2 MCU Connector
        3. 3.5.17.3 PRU Connector
      18. 3.5.18 Push Buttons
      19. 3.5.19 I2C Address Mapping
  6. 4Known Issues and Modifications
  7. 5Revision History
  8. 6IMPORTANT NOTICE AND DISCLAIMER

3.5.16.2 Boot Modes

The boot mode for the AM62x-Low power SK EVM board is defined by two banks of switches SW3 and SW4 or by the I2C buffer connected to the Test automation connector. This allows for AM62x SoC Boot mode control by either the user (DIP Switch Control) or by the Test Automation connector.

All the bits of switch (SW3 & SW4) have week pull down resistor and a strong pull up resistor as shown in below picture. Note that OFF setting provides a low logic level (‘0’) and an ON setting provides a high logic level (‘1’).

GUID-20230616-SS0I-2JD5-RL0J-DP64GD5RRBTJ-low.png

The boot mode pins of the SoC have associated alternate functions during normal operation. Hence isolation isprovided using Buffer IC’s to cater for alternate pin functionality. The output of the buffer is connected to the bootmode pins on the AM62x Low Power SK EVM. The output is enabled when the bootmode is needed during a reset cycle.

The input to the buffer is connected to the DIP switch circuit and to the output of an I2C buffer set by the test automatio ncircuit. If the test automation circuit is going to control the bootmode, all the switches will manually be set to the OFF position. The bootmode buffer should be powered by an always ON power supply to ensure that the bootmode remains present even if the SoC power is cycled.

Switch SW1 and SW2 bits [15:0] are used to set the SoC Boot mode.

The switch map to the boot mode functions is provided in the tables below.

Figure 3-27 Boot Mode Switch Example
Table 3-17 Boot Mode Pin Mapping
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Reserved Backup Boot Mode Configuration Backup Boot Mode Primary Boot Mode Configuration Primary Boot Mode PLL Configuration

BOOT-MODE[0:2] – Denote system clock frequency for PLL configuration. By default this bits are set for 25MHz.

Table 3-18 PLL Reference Clock Selection
SW3.3 SW3.2 SW3.1 PLL REF CLK (MHz)
OFF OFF OFF RSVD
OFF OFF ON RSVD
OFF ON OFF 24
OFF ON ON 25
ON OFF OFF 26
ON OFF ON RSVD
ON ON OFF RSVD
ON ON ON RSVD

BOOT-MODE [3:6] – This provides primary boot mode configuration to select the requested boot mode after POR, that is, the peripheral/memory to boot from primary boot device selection details.

Table 3-19 Boot Device Selection BOOT-MODE [6:3]
SW3.7 SW3.6 SW3.5 SW3.4 Primary Boot Device Selected
OFF OFF OFF OFF Serial NAND
OFF OFF OFF ON OSPI
OFF OFF ON OFF QSPI
OFF OFF ON ON SPI
OFF ON OFF OFF Ethernet RGMII1
OFF ON OFF ON Ethernet RMII1
OFF ON ON OFF I2C
OFF ON ON ON UART
ON OFF OFF OFF MMC/SD card
ON OFF OFF ON eMMC
ON OFF ON OFF USB0
ON OFF ON ON GPMC NAND
ON ON OFF OFF GPMC NOR
ON ON OFF ON Rsvd
ON ON ON OFF xSPI
ON ON ON ON No boot/Dev Boot

• BOOT-MODE [10:12] – Select the backup boot mode, used when the primary boot mode is not available.

Table 3-20 Backup Boot Mode Selection BOOT-MODE [12:10]
SW4.5 SW4.4 SW4.3 Backup Boot Device Selected
OFF OFF OFF None(No backup mode)
OFF OFF ON USB
OFF ON OFF Reserved
OFF ON ON UART
ON OFF OFF Ethernet
ON OFF ON MMC/SD
ON ON OFF SPI
ON ON ON I2C

BOOT-MODE [9:7] – These pins provide optional settings and are used in conjunction with the primary boot device selected.

Table 3-21 Primary Boot Media Configuration BOOT-MODE[9:7]
SW4.2 SW4.1 SW3.8 Boot Device
Reserved Read Mode 2 Read Mode 1 Serial NAND
Reserved Iclk Csel QSPI
Speed Iclk Csel OSPI
Reserved Mode Csel SPI
Clkout 0 Link stat Ethernet RGMII
Clkout Clk src 0 Ethernet RMII
Bus Reset Reserved Addr I2C
Reserved Reserved Reserved UART
Port Reserved Fs/raw MMC/ SD card
Reserved Reserved Reserved eMMC
Core Volt Mode Lane swap USB0
Reserved Reserved Reserved GPMC NAND
Reserved Reserved Reserved GPMC NOR
Reserved Reserved Reserved Reserved
SFDP Read Cmd Mode xSPI
Reserved ARM/Thumb No/Dev No boot/Dev Boot

BOOT-MODE[13] – These pins provide optional settings and are used in conjunction with the backup boot device devices. Switch SW2.6 when ON sets 1 and sets 0 if OFF, see the device-specific TRM.

BOOT-MODE [14:15] – Reserved. Provides backup boot media configuration options.

Table 3-22 Backup Boot Media Configuration BOOT-MODE[13]
SW4.6 Boot Device
Reserved None
Mode USB
Reserved Reserved
Reserved UART
IF Ethernet
Port MMC/SD
Reserved SPI
Reserved I2C