SPRUJ51 june   2023

 

  1.   1
  2. 1Abstract
  3. 2EVM Revisions and Assembly Variants
    1. 2.1 Inside the Box
    2. 2.2 EMC, EMI and ESD Compliance
  4.   Trademarks
  5. 3System Description
    1. 3.1 Key Features
      1. 3.1.1 Processor
      2. 3.1.2 Power Supply
      3. 3.1.3 Memory
      4. 3.1.4 JTAG Emulator
      5. 3.1.5 Supported Interfaces and Peripherals
      6. 3.1.6 Expansion Connectors Headers to Support Application Specific Add On Boards
    2. 3.2 Functional Block Diagram
    3. 3.3 AM62x-Low Power SK EVM Interface Mapping
    4. 3.4 Power ON OFF Procedures
      1. 3.4.1 Power-On Procedure
      2. 3.4.2 Power-Off Procedure
      3. 3.4.3 Power Test Points
    5. 3.5 Peripheral and Major Component Description
      1. 3.5.1  Clocking
      2. 3.5.2  Reset
      3. 3.5.3  OLDI Display Interface
      4. 3.5.4  CSI Interface
      5. 3.5.5  Audio Codec Interface
      6. 3.5.6  HDMI Display Interface
      7. 3.5.7  JTAG Interface
      8. 3.5.8  Test Automation Header
      9. 3.5.9  UART Interface
      10. 3.5.10 USB Interface
        1. 3.5.10.1 USB 2.0 Type A Interface
        2. 3.5.10.2 USB 2.0 Type C Interface
      11. 3.5.11 Memory Interfaces
        1. 3.5.11.1 LPDDR4 Interface
        2. 3.5.11.2 OSPI Interface
        3. 3.5.11.3 MMC Interfaces
          1. 3.5.11.3.1 MMC0 - eMMC Interface
          2. 3.5.11.3.2 MMC1 - Micro SD Interface
          3. 3.5.11.3.3 MMC2 - M2 Key E Interface
        4. 3.5.11.4 EEPROM
      12. 3.5.12 Ethernet Interface
        1. 3.5.12.1 CPSW Ethernet PHY1 Default Configuration
        2. 3.5.12.2 CPSW Ethernet PHY2 Default Configuration
      13. 3.5.13 GPIO Port Expander
      14. 3.5.14 GPIO Mapping
      15. 3.5.15 Power
        1. 3.5.15.1 Power Requirements
        2. 3.5.15.2 Power Input
        3. 3.5.15.3 Power Supply
        4. 3.5.15.4 Power Sequencing
        5. 3.5.15.5 AM62x 17x17 SoC Power
        6. 3.5.15.6 Current Monitoring
      16. 3.5.16 AM62x-Low Power SK EVM User Setup and Configuration
        1. 3.5.16.1 EVM DIP Switches
        2. 3.5.16.2 Boot Modes
        3. 3.5.16.3 User Test LEDs
      17. 3.5.17 Expansion Headers
        1. 3.5.17.1 User Expansion Connector
        2. 3.5.17.2 MCU Connector
        3. 3.5.17.3 PRU Connector
      18. 3.5.18 Push Buttons
      19. 3.5.19 I2C Address Mapping
  6. 4Known Issues and Modifications
  7. 5Revision History
  8. 6IMPORTANT NOTICE AND DISCLAIMER

3.5.4 CSI Interface

The CSI-2 interface from the AM62x 17x17 SoC is terminated to a 40 pin Camera MIPI connector QSH-020-01-L-D-DP-A-K. The SoC supports 4 CSI RX Lanes, four are pinned out on the SKEVM. The table below contains 40 pin Camera MIPI connector pin-out. SoC I2C2 signals are also connected to the CSI Header. IO Expander GPIO signals are connected to the camera GPIO’s.
GUID-20230519-SS0I-QTKF-WKMJ-GTSKC0DMFGJP-low.png Figure 3-10 CSI Interface Block Diagram
Table 3-5 CSI Camera Connector J19 Pinout
Pin No Pin Description Pin No Pin Description
1 NC 21 CSI0_RXP3
2 CSI_I2C2_SCL_BUFF 22 CSI_GPIO4_buff
3 NC 23 CSI0_RXN3
4 CSI_I2C2_SDA_BUFF 24 Ground
5 CSI0_RXCLKP 25 NC
6 CSI_GPIO0_buff 26 NC
7 CSI0_RXCLKN 27 NC
8 CSI_GPIO1_buff 28 NC
9 CSI0_RXP0 29 NC
10 CSI_REFCLK 30 VCC_3V3_SYS
11 CSI0_RXN0 31 NC
12 Ground 32 VCC_3V3_SYS
13 CSI0_RXP1 33 NC
14 CSI_RSTz_buff 34 VCC_3V3_SYS
15 CSI0_RXN1 35 NC
16 Ground 36 VCC_3V3_SYS
17 CSI0_RXP2 37 NC
18 CSI_GPIO2_buff 38 VCC_CSI_IO
19 CSI0_RXN2 39 NC
20 CSI_GPIO3_buff 40 VCC_CSI_IO