SPRUJ51 june   2023

 

  1.   1
  2. 1Abstract
  3. 2EVM Revisions and Assembly Variants
    1. 2.1 Inside the Box
    2. 2.2 EMC, EMI and ESD Compliance
  4.   Trademarks
  5. 3System Description
    1. 3.1 Key Features
      1. 3.1.1 Processor
      2. 3.1.2 Power Supply
      3. 3.1.3 Memory
      4. 3.1.4 JTAG Emulator
      5. 3.1.5 Supported Interfaces and Peripherals
      6. 3.1.6 Expansion Connectors Headers to Support Application Specific Add On Boards
    2. 3.2 Functional Block Diagram
    3. 3.3 AM62x-Low Power SK EVM Interface Mapping
    4. 3.4 Power ON OFF Procedures
      1. 3.4.1 Power-On Procedure
      2. 3.4.2 Power-Off Procedure
      3. 3.4.3 Power Test Points
    5. 3.5 Peripheral and Major Component Description
      1. 3.5.1  Clocking
      2. 3.5.2  Reset
      3. 3.5.3  OLDI Display Interface
      4. 3.5.4  CSI Interface
      5. 3.5.5  Audio Codec Interface
      6. 3.5.6  HDMI Display Interface
      7. 3.5.7  JTAG Interface
      8. 3.5.8  Test Automation Header
      9. 3.5.9  UART Interface
      10. 3.5.10 USB Interface
        1. 3.5.10.1 USB 2.0 Type A Interface
        2. 3.5.10.2 USB 2.0 Type C Interface
      11. 3.5.11 Memory Interfaces
        1. 3.5.11.1 LPDDR4 Interface
        2. 3.5.11.2 OSPI Interface
        3. 3.5.11.3 MMC Interfaces
          1. 3.5.11.3.1 MMC0 - eMMC Interface
          2. 3.5.11.3.2 MMC1 - Micro SD Interface
          3. 3.5.11.3.3 MMC2 - M2 Key E Interface
        4. 3.5.11.4 EEPROM
      12. 3.5.12 Ethernet Interface
        1. 3.5.12.1 CPSW Ethernet PHY1 Default Configuration
        2. 3.5.12.2 CPSW Ethernet PHY2 Default Configuration
      13. 3.5.13 GPIO Port Expander
      14. 3.5.14 GPIO Mapping
      15. 3.5.15 Power
        1. 3.5.15.1 Power Requirements
        2. 3.5.15.2 Power Input
        3. 3.5.15.3 Power Supply
        4. 3.5.15.4 Power Sequencing
        5. 3.5.15.5 AM62x 17x17 SoC Power
        6. 3.5.15.6 Current Monitoring
      16. 3.5.16 AM62x-Low Power SK EVM User Setup and Configuration
        1. 3.5.16.1 EVM DIP Switches
        2. 3.5.16.2 Boot Modes
        3. 3.5.16.3 User Test LEDs
      17. 3.5.17 Expansion Headers
        1. 3.5.17.1 User Expansion Connector
        2. 3.5.17.2 MCU Connector
        3. 3.5.17.3 PRU Connector
      18. 3.5.18 Push Buttons
      19. 3.5.19 I2C Address Mapping
  6. 4Known Issues and Modifications
  7. 5Revision History
  8. 6IMPORTANT NOTICE AND DISCLAIMER

3.5.12.1 CPSW Ethernet PHY1 Default Configuration

The default configuration of the DP83867 is determined using a number of resistor pull-up and pull-down values on specific pins of the PHY. Depending on the values installed, each of the configuration pins can be set to one of four modes by using the pull up and pull down options provided. The AM62x-Low Power SK EVM uses the 48-pin QFN package which supports the RGMII interface.

The DP83867 PHY uses four level configurations based on resistor strapping which generate four distinct voltagesranges. The resistors are connected to the RX data and control pins which are normally driven by the PHY and are inputs to the processor. The voltage range for each mode is shown below

Mode1 - 0V to 0.3V

Mode 2 – 0.462V to 0.6303V

Mode3 – 0.7425V to 0.9372V

Mode4 – 2.2902V to 2.9304V

Footprints for both pull-up and pull-down is provided on all the strapping pins except LED_0. LED_0 is for Mirror Enable, which is set to mode 1 by default, Mode 4 is not applicable and Mode2, Mode3 option is not desired.CPSW_RGMII1 port of the AM62X 17x17 SoC is connected to DP83867 whose configuration is as given below.

PHY ADDR: 00000

Auto_neg: Disabled

ANG_sel: 10/100/1000

RGMIIClk skew Tx: 0ns

RGMIIClk skew Rx: 2ns

Table 3-9 CPSW Ethernet PHY–1 Strap values
Strap SettingPin NameStrap FunctionModeValueof Strap FunctionDescription

PHY Address

RX_D2

PHY_AD310

PHY Address: 0000

PHY_AD210

RX_D0

PHY_AD110
PHY_AD010
Auto NegotiationRX_DV/ RX_CTRLAuto- neg30Autoneg Disabled

Modes of Operation

LED2

RGMIIClock Skew TX[1]50

RGMIITX Clock Skew is set to 0 ns

RGMIIClock Skew TX[0]50

LED_1

RGMIIClock Skew TX[2]51
ANEG_SEL10advertiseability of 10/100/1000
LED_0Mirror Enable10Mirror Enable Disabled

GPIO_1

RGMIIClock Skew RX[2]10

RGMIIRX Clock Skew is set to 2 ns

RGMIIClock Skew RX[1]10
GPIO_0RGMIIClock Skew RX[0]10