SPRUJ53B April 2024 – September 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1
Table 31-7 lists the memory-mapped registers for the AES_REGS registers. All register offset addresses not listed in Table 31-7 should be considered as reserved locations and the register contents should not be modified.
| Offset | Acronym | Register Name | Write Protection | Section |
|---|---|---|---|---|
| 0h | AES_KEY2_6 | XTS Second Key or CBC-MAC Third Key | Go | |
| 4h | AES_KEY2_7 | XTS Second Key or CBC-MAC Third Key | Go | |
| 8h | AES_KEY2_4 | XTS/CCM Second Key or CBC-MAC Third Key | Go | |
| Ch | AES_KEY2_5 | XTS Second Key or CBC-MAC Third Key | Go | |
| 10h | AES_KEY2_2 | XTS/CCM/CBC-MAC Second Key or Hash Key Input | Go | |
| 14h | AES_KEY2_3 | XTS/CCM/CBC-MAC Second Key or Hash Key Input | Go | |
| 18h | AES_KEY2_0 | XTS/CCM/CBC-MAC Second Key or Hash Key Input | Go | |
| 1Ch | AES_KEY2_1 | XTS/CCM/CBC-MAC Second Key or Hash Key Input | Go | |
| 20h | AES_KEY1_6 | Key | Go | |
| 24h | AES_KEY1_7 | Key | Go | |
| 28h | AES_KEY1_4 | Key | Go | |
| 2Ch | AES_KEY1_5 | Key | Go | |
| 30h | AES_KEY1_2 | Key | Go | |
| 34h | AES_KEY1_3 | Key | Go | |
| 38h | AES_KEY1_0 | Key | Go | |
| 3Ch | AES_KEY1_1 | Key | Go | |
| 40h | AES_IV_IN_OUT_0 | Initialization Vector 0 | Go | |
| 44h | AES_IV_IN_OUT_1 | Initialization Vector 1 | Go | |
| 48h | AES_IV_IN_OUT_2 | Initialization Vector 2 | Go | |
| 4Ch | AES_IV_IN_OUT_3 | Initialization Vector 3 | Go | |
| 50h | AES_CTRL | Input/Output Buffer Control and Mode Selection | Go | |
| 54h | AES_C_LENGTH_0 | Crypto Data Length 0 | Go | |
| 58h | AES_C_LENGTH_1 | Crypto Data Length 1 | Go | |
| 5Ch | AES_AUTH_LENGTH | AAD Data Length | Go | |
| 60h | AES_DATA_IN_OUT_0 | Data Word 0 | Go | |
| 64h | AES_DATA_IN_OUT_1 | Data Word 1 | Go | |
| 68h | AES_DATA_IN_OUT_2 | Data Word 2 | Go | |
| 6Ch | AES_DATA_IN_OUT_3 | Data Word 3 | Go | |
| 70h | AES_TAG_OUT_0 | Hash Result 0 | Go | |
| 74h | AES_TAG_OUT_1 | Hash Result 1 | Go | |
| 78h | AES_TAG_OUT_2 | Hash Result 2 | Go | |
| 7Ch | AES_TAG_OUT_3 | Hash Result 3 | Go | |
| 80h | AES_REV | Module Revision Number | Go | |
| 84h | AES_SYSCONFIG | System Configuration | Go | |
| 88h | AES_SYSSTATUS | Reset Status | Go | |
| 8Ch | AES_IRQSTATUS | Interrupt Status | Go | |
| 90h | AES_IRQENABLE | Interrupt Enable | Go | |
| 94h | AES_DIRTY_BITS | Accessed / Dirty Bits | Go |
Complex bit access types are encoded to fit into small table cells. Table 31-8 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| R-0 | R -0 | Read Returns 0s |
| Write Type | ||
| W | W | Write |
| W1S | W 1S | Write 1 to set |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |
| Register Array Variables | ||
| i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
| y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. | |
AES_KEY2_6 is shown in Figure 31-14 and described in Table 31-9.
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Secure Host Interface Bank
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| KEY | |||||||||||||||||||||||||||||||
| R-0/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | KEY | R-0/W | 0h | Key Data This register contains the 32-bit key data for the AES module. Initial key for XTS operations For a Host write operation, these registers must be written with the 128, 192 or 256-bit key for a subsequent AES operation. The key size equals the AES_KEY1 size. For a Host write operation, these registers must be written with the new values to be subsequently transferred to the AES Engine. OR Pre-calculated CBC-MAC third key (K3), used to perform a final XOR operation on the last input data block. OR This register is used to store intermediate values and must be initialized with zeroes when writing a new GCM context. OR Used in f8/f9 algorithm Reset type: PER.RESET |
AES_KEY2_7 is shown in Figure 31-15 and described in Table 31-10.
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Secure Host Interface Bank MSW for CBC-MAC and 256-bit XTS
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| KEY | |||||||||||||||||||||||||||||||
| R-0/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | KEY | R-0/W | 0h | Key Data This register contains the 32-bit key data for the AES module. Initial key for XTS operations For a Host write operation, these registers must be written with the 128, 192 or 256-bit key for a subsequent AES operation. The key size equals the AES_KEY1 size. For a Host write operation, these registers must be written with the new values to be subsequently transferred to the AES Engine. OR Pre-calculated CBC-MAC third key (K3), used to perform a final XOR operation on the last input data block. Reset type: PER.RESET |
AES_KEY2_4 is shown in Figure 31-16 and described in Table 31-11.
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Secure Host Interface Bank LSW for CBC-MAC
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| KEY | |||||||||||||||||||||||||||||||
| R-0/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | KEY | R-0/W | 0h | Key Data This register contains the 32-bit key data for the AES module. Initial key for XTS operations For a Host write operation, these registers must be written with the 128, 192 or 256-bit key for a subsequent AES operation. The key size equals the AES_KEY1 size. For a Host write operation, these registers must be written with the new values to be subsequently transferred to the AES Engine. OR Pre-calculated CBC-MAC third key (K3), used to perform a final XOR operation on the last input data block. Reset type: PER.RESET |
AES_KEY2_5 is shown in Figure 31-17 and described in Table 31-12.
Return to the Summary Table.
Secure Host Interface Bank MSW for 192-bit XTS
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| KEY | |||||||||||||||||||||||||||||||
| R-0/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | KEY | R-0/W | 0h | Key Data This register contains the 32-bit key data for the AES module. Initial key for XTS operations For a Host write operation, these registers must be written with the 128, 192 or 256-bit key for a subsequent AES operation. The key size equals the AES_KEY1 size. For a Host write operation, these registers must be written with the new values to be subsequently transferred to the AES Engine. OR Pre-calculated CBC-MAC third key (K3), used to perform a final XOR operation on the last input data block. Reset type: PER.RESET |
AES_KEY2_2 is shown in Figure 31-18 and described in Table 31-13.
Return to the Summary Table.
Secure Host Interface Bank
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| KEY | |||||||||||||||||||||||||||||||
| R-0/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | KEY | R-0/W | 0h | Key Data This register contains the 32-bit key data for the AES module. Initial key for XTS operations For a Host write operation, these registers must be written with the 128, 192 or 256-bit key for a subsequent AES operation. The key size equals the AES_KEY1 size. For a Host write operation, these registers must be written with the new values to be subsequently transferred to the AES Engine. OR Pre-calculated CBC-MAC second key (K2), used to perform a final XOR operation on the last input data block. OR Hash key, can be calculated internal or written via these registers. Only used for GHASH (GCM) modes. For a Host write operation, these registers must be written with the new values to be subsequently transferred to the AES Engine. OR These 128-bits are used to store the CKKM / IKKM value for f8 OR These 128-bits are used to store the CKKM / IKKM value for f9 Reset type: PER.RESET |
AES_KEY2_3 is shown in Figure 31-19 and described in Table 31-14.
Return to the Summary Table.
Secure Host Interface Bank MSW for CCM, CBC-MAC, Hash Key, and 128-bit XTS
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| KEY | |||||||||||||||||||||||||||||||
| R-0/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | KEY | R-0/W | 0h | Key Data This register contains the 32-bit key data for the AES module. Initial key for XTS operations For a Host write operation, these registers must be written with the 128, 192 or 256-bit key for a subsequent AES operation. The key size equals the AES_KEY1 size. For a Host write operation, these registers must be written with the new values to be subsequently transferred to the AES Engine. OR Pre-calculated CBC-MAC second key (K2), used to perform a final XOR operation on the last input data block. OR Hash key, can be calculated internal or written via these registers. Only used for GHASH (GCM) modes. For a Host write operation, these registers must be written with the new values to be subsequently transferred to the AES Engine. OR These 128-bits are used to store the CKKM / IKKM value for f8 OR These 128-bits are used to store the CKKM / IKKM value for f9 Reset type: PER.RESET |
AES_KEY2_0 is shown in Figure 31-20 and described in Table 31-15.
Return to the Summary Table.
Secure Host Interface Bank LSW for XTS, CCM, CBC-MAC, and Hash Key
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| KEY | |||||||||||||||||||||||||||||||
| R-0/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | KEY | R-0/W | 0h | Key Data This register contains the 32-bit key data for the AES module. Initial key for XTS operations For a Host write operation, these registers must be written with the 128, 192 or 256-bit key for a subsequent AES operation. The key size equals the AES_KEY1 size. For a Host write operation, these registers must be written with the new values to be subsequently transferred to the AES Engine. OR Pre-calculated CBC-MAC second key (K2), used to perform a final XOR operation on the last input data block. OR Hash key, can be calculated internal or written via these registers. Only used for GHASH (GCM) modes. For a Host write operation, these registers must be written with the new values to be subsequently transferred to the AES Engine. OR These 128-bits are used to store the CKKM / IKKM value for f8 OR These 128-bits are used to store the CKKM / IKKM value for f9 Reset type: PER.RESET |
AES_KEY2_1 is shown in Figure 31-21 and described in Table 31-16.
Return to the Summary Table.
Secure Host Interface Bank
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| KEY | |||||||||||||||||||||||||||||||
| R-0/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | KEY | R-0/W | 0h | Key Data This register contains the 32-bit key data for the AES module. Initial key for XTS operations For a Host write operation, these registers must be written with the 128, 192 or 256-bit key for a subsequent AES operation. The key size equals the AES_KEY1 size. For a Host write operation, these registers must be written with the new values to be subsequently transferred to the AES Engine. OR Pre-calculated CBC-MAC second key (K2), used to perform a final XOR operation on the last input data block. OR Hash key, can be calculated internal or written via these registers. Only used for GHASH (GCM) modes. For a Host write operation, these registers must be written with the new values to be subsequently transferred to the AES Engine. OR These 128-bits are used to store the CKKM / IKKM value for f8 OR These 128-bits are used to store the CKKM / IKKM value for f9 Reset type: PER.RESET |
AES_KEY1_6 is shown in Figure 31-22 and described in Table 31-17.
Return to the Summary Table.
Secure Host Interface Bank
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| KEY | |||||||||||||||||||||||||||||||
| R-0/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | KEY | R-0/W | 0h | AES Key register. For a Host write operation, these registers must be written with the 128, 192 or 256-bit key for a subsequent AES operation. For a Host read operation, these registers return all-zeroes. The Host will typically write these registers in order, beginning with the AES_KEY_0 register. The key size (see the AES_MODE register) determines which key registers need to be populated, as indicated in the table below. Reset type: PER.RESET |
AES_KEY1_7 is shown in Figure 31-23 and described in Table 31-18.
Return to the Summary Table.
Secure Host Interface Bank MSW for 256-bit key
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| KEY | |||||||||||||||||||||||||||||||
| R-0/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | KEY | R-0/W | 0h | AES Key register. For a Host write operation, these registers must be written with the 128, 192 or 256-bit key for a subsequent AES operation. For a Host read operation, these registers return all-zeroes. The Host will typically write these registers in order, beginning with the AES_KEY_0 register. The key size (see the AES_MODE register) determines which key registers need to be populated, as indicated in the table below. Reset type: PER.RESET |
AES_KEY1_4 is shown in Figure 31-24 and described in Table 31-19.
Return to the Summary Table.
Secure Host Interface Bank
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| KEY | |||||||||||||||||||||||||||||||
| R-0/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | KEY | R-0/W | 0h | AES Key register. For a Host write operation, these registers must be written with the 128, 192 or 256-bit key for a subsequent AES operation. For a Host read operation, these registers return all-zeroes. The Host will typically write these registers in order, beginning with the AES_KEY_0 register. The key size (see the AES_MODE register) determines which key registers need to be populated, as indicated in the table below. Reset type: PER.RESET |
AES_KEY1_5 is shown in Figure 31-25 and described in Table 31-20.
Return to the Summary Table.
Secure Host Interface Bank MSW for 192-bit key
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| KEY | |||||||||||||||||||||||||||||||
| R-0/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | KEY | R-0/W | 0h | AES Key register. For a Host write operation, these registers must be written with the 128, 192 or 256-bit key for a subsequent AES operation. For a Host read operation, these registers return all-zeroes. The Host will typically write these registers in order, beginning with the AES_KEY_0 register. The key size (see the AES_MODE register) determines which key registers need to be populated, as indicated in the table below. Reset type: PER.RESET |
AES_KEY1_2 is shown in Figure 31-26 and described in Table 31-21.
Return to the Summary Table.
Secure Host Interface Bank
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| KEY | |||||||||||||||||||||||||||||||
| R-0/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | KEY | R-0/W | 0h | AES Key register. For a Host write operation, these registers must be written with the 128, 192 or 256-bit key for a subsequent AES operation. For a Host read operation, these registers return all-zeroes. The Host will typically write these registers in order, beginning with the AES_KEY_0 register. The key size (see the AES_MODE register) determines which key registers need to be populated, as indicated in the table below. Reset type: PER.RESET |
AES_KEY1_3 is shown in Figure 31-27 and described in Table 31-22.
Return to the Summary Table.
Secure Host Interface Bank MSW for 128-bit key
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| KEY | |||||||||||||||||||||||||||||||
| R-0/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | KEY | R-0/W | 0h | AES Key register. For a Host write operation, these registers must be written with the 128, 192 or 256-bit key for a subsequent AES operation. For a Host read operation, these registers return all-zeroes. The Host will typically write these registers in order, beginning with the AES_KEY_0 register. The key size (see the AES_MODE register) determines which key registers need to be populated, as indicated in the table below. Reset type: PER.RESET |
AES_KEY1_0 is shown in Figure 31-28 and described in Table 31-23.
Return to the Summary Table.
Secure Host Interface Bank LSW
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| KEY | |||||||||||||||||||||||||||||||
| R-0/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | KEY | R-0/W | 0h | AES Key register. For a Host write operation, these registers must be written with the 128, 192 or 256-bit key for a subsequent AES operation. For a Host read operation, these registers return all-zeroes. The Host will typically write these registers in order, beginning with the AES_KEY_0 register. The key size (see the AES_MODE register) determines which key registers need to be populated, as indicated in the table below. Reset type: PER.RESET |
AES_KEY1_1 is shown in Figure 31-29 and described in Table 31-24.
Return to the Summary Table.
Secure Host Interface Bank
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| KEY | |||||||||||||||||||||||||||||||
| R-0/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | KEY | R-0/W | 0h | AES Key register. For a Host write operation, these registers must be written with the 128, 192 or 256-bit key for a subsequent AES operation. For a Host read operation, these registers return all-zeroes. The Host will typically write these registers in order, beginning with the AES_KEY_0 register. The key size (see the AES_MODE register) determines which key registers need to be populated, as indicated in the table below. Reset type: PER.RESET |
AES_IV_IN_OUT_0 is shown in Figure 31-30 and described in Table 31-25.
Return to the Summary Table.
Secure Host Interface Bank LSW
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DATA | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | DATA | R/W | 0h | For a Host write operation, these registers must be written with the new 128-bit IV to be subsequently transferred to the AES Engine. For a Host read operation, these registers contain the latest 128-bit IV output by the AES Engine. This value is incremented with 0x1, after first use when a new data block is submitted to the engine if CTR/ICM mode is selected. OR For XTS mode, this register must be written with the tweak location i of the data unit or (intermediate) tweak value (Tj), For a Host read operation, the IV_OUT register holds the next tweak value that is used for the next data block provided via the DATA_IN registers. This value can be re-used for continuation with the next block. It must be provide together with a 'j' of '0' via the IV_IN registers. OR For f8 this field must be written with zeroes. OR (In case of GCM) For a Host write operation, these registers must be written with the new 128-bit IV to be subsequently transferred to the AES Engine. For a Host read operation, these registers contain the latest 128-bit IV output by the AES Engine. Note that bits [127:96] of the IV represent the initial counter value (which is '1' for GCM) and must therefore be initialized to 0x01000000. This value is incremented with 0x1, after first use when a new data block is submitted to the engine. OR For CCM this field must be written with A0, this value constist of the concatenation of: A0-flags (5-bits of zero and 3-bits 'L'), Nonce and counter value. 'L' must be a copy from the 'L' value of the AES_CTRL register. This 'L' indicates the width of the Nonce and counter. The loaded counter must be initialized to zero. The total width of A0 is 128-bit. Reset type: PER.RESET |
AES_IV_IN_OUT_1 is shown in Figure 31-31 and described in Table 31-26.
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Secure Host Interface Bank
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DATA | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | DATA | R/W | 0h | For a Host write operation, these registers must be written with the new 128-bit IV to be subsequently transferred to the AES Engine. For a Host read operation, these registers contain the latest 128-bit IV output by the AES Engine. This value is incremented with 0x1, after first use when a new data block is submitted to the engine if CTR/ICM mode is selected. OR For XTS mode, this register must be written with the tweak location i of the data unit or (intermediate) tweak value (Tj), For a Host read operation, the IV_OUT register holds the next tweak value that is used for the next data block provided via the DATA_IN registers. This value can be re-used for continuation with the next block. It must be provide together with a 'j' of '0' via the IV_IN registers. OR For f8 this field must be written with zeroes. OR (In case of GCM) For a Host write operation, these registers must be written with the new 128-bit IV to be subsequently transferred to the AES Engine. For a Host read operation, these registers contain the latest 128-bit IV output by the AES Engine. Note that bits [127:96] of the IV represent the initial counter value (which is '1' for GCM) and must therefore be initialized to 0x01000000. This value is incremented with 0x1, after first use when a new data block is submitted to the engine. OR For CCM this field must be written with A0, this value constist of the concatenation of: A0-flags (5-bits of zero and 3-bits 'L'), Nonce and counter value. 'L' must be a copy from the 'L' value of the AES_CTRL register. This 'L' indicates the width of the Nonce and counter. The loaded counter must be initialized to zero. The total width of A0 is 128-bit. Reset type: PER.RESET |
AES_IV_IN_OUT_2 is shown in Figure 31-32 and described in Table 31-27.
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Secure Host Interface Bank
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DATA | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | DATA | R/W | 0h | For a Host write operation, these registers must be written with the new 128-bit IV to be subsequently transferred to the AES Engine. For a Host read operation, these registers contain the latest 128-bit IV output by the AES Engine. This value is incremented with 0x1, after first use when a new data block is submitted to the engine if CTR/ICM mode is selected. OR For XTS mode, this register must be written with the tweak location i of the data unit or (intermediate) tweak value (Tj), For a Host read operation, the IV_OUT register holds the next tweak value that is used for the next data block provided via the DATA_IN registers. This value can be re-used for continuation with the next block. It must be provide together with a 'j' of '0' via the IV_IN registers. OR For f8 this field must be written with zeroes. OR (In case of GCM) For a Host write operation, these registers must be written with the new 128-bit IV to be subsequently transferred to the AES Engine. For a Host read operation, these registers contain the latest 128-bit IV output by the AES Engine. Note that bits [127:96] of the IV represent the initial counter value (which is '1' for GCM) and must therefore be initialized to 0x01000000. This value is incremented with 0x1, after first use when a new data block is submitted to the engine. OR For CCM this field must be written with A0, this value constist of the concatenation of: A0-flags (5-bits of zero and 3-bits 'L'), Nonce and counter value. 'L' must be a copy from the 'L' value of the AES_CTRL register. This 'L' indicates the width of the Nonce and counter. The loaded counter must be initialized to zero. The total width of A0 is 128-bit. Reset type: PER.RESET |
AES_IV_IN_OUT_3 is shown in Figure 31-33 and described in Table 31-28.
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Secure Host Interface Bank MSW
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DATA | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | DATA | R/W | 0h | For a Host write operation, these registers must be written with the new 128-bit IV to be subsequently transferred to the AES Engine. For a Host read operation, these registers contain the latest 128-bit IV output by the AES Engine. This value is incremented with 0x1, after first use when a new data block is submitted to the engine if CTR/ICM mode is selected. OR For XTS mode, this register must be written with the tweak location i of the data unit or (intermediate) tweak value (Tj), For a Host read operation, the IV_OUT register holds the next tweak value that is used for the next data block provided via the DATA_IN registers. This value can be re-used for continuation with the next block. It must be provide together with a 'j' of '0' via the IV_IN registers. OR For f8 this field must be written with zeroes. OR (In case of GCM) For a Host write operation, these registers must be written with the new 128-bit IV to be subsequently transferred to the AES Engine. For a Host read operation, these registers contain the latest 128-bit IV output by the AES Engine. Note that bits [127:96] of the IV represent the initial counter value (which is '1' for GCM) and must therefore be initialized to 0x01000000. This value is incremented with 0x1, after first use when a new data block is submitted to the engine. OR For CCM this field must be written with A0, this value constist of the concatenation of: A0-flags (5-bits of zero and 3-bits 'L'), Nonce and counter value. 'L' must be a copy from the 'L' value of the AES_CTRL register. This 'L' indicates the width of the Nonce and counter. The loaded counter must be initialized to zero. The total width of A0 is 128-bit. Reset type: PER.RESET |
AES_CTRL is shown in Figure 31-34 and described in Table 31-29.
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Secure Host Interface Bank
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| CTXTRDY | SVCTXTRDY | SAVE_CONTEXT | RESERVED | CCM_M | |||
| R-1h | R-0h | R/W-0h | R-0h | R/W-0h | |||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| CCM_M | CCM_L | CCM | GCM | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CBCMAC | F9 | F8 | XTS | CFB | ICM | CTR_WIDTH | |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CTR_WIDTH | CTR | MODE | KEY_SIZE | DIRECTION | INPUT_READY | OUTPUT_READY | |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0h | R-0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | CTXTRDY | R | 1h | Context Data Registers Ready Value Description 0 The context data registers are not ready to be overwritten. 1 The context data registers can be overwritten and the host is permitted to write the next context. Reset type: PER.RESET |
| 30 | SVCTXTRDY | R | 0h | AES TAG/IV Block(s) Ready This bit is only asserted if the SAVE_CONTEXT bit is set to 1. This bit is mutual exclusive with the CTXTRDY bit. Value Description 0 AES authentication TAG and/or IV block(s) is/are not available. 1 Indicates the AES authentication TAG and /or IV block(s) is/are available for the host to retrieve. Reset type: PER.RESET |
| 29 | SAVE_CONTEXT | R/W | 0h | TAG or Result IV Save If this bit is set, the CONTEXT_OUT interrupt bit is set in the AES_IRQSTATUS register if the operation is finished and related signals are enabled. Value Description 0 No effect. 1 Indicates an authentication TAG of result IV needs to be stored as a result context. Reset type: PER.RESET |
| 28-25 | RESERVED | R | 0h | Reserved |
| 24-22 | CCM_M | R/W | 0h | Counter with CBC-MAC (CCM)Defines M which indicates the length of the authentication field for CCM operations the authentication field length equals two times the sum of CCM-M plus one. The AES Engine always returns a 128-bit authentication field, of which the M least significant bytes are valid. All values are supported. Reset type: PER.RESET |
| 21-19 | CCM_L | R/W | 0h | Indicates the width of the length field for CCM operations the length field in bytes equals the value of CMM-L plus one. Supported values for L are: Value Description 0x0 width = 0 0x1 width = 2 0x2 reserved 0x3 width = 4 0x4 - 0x6 reserved 0x7 width = 8 Reset type: PER.RESET |
| 18 | CCM | R/W | 0h | AES-CCM Mode Enable Value Description 0 AES-CCM mode is not enabled. 1 AES-CCM mode enabled. This is a combined mode, using AES for both authentication and encryption. No additional mode selection is required. Reset type: PER.RESET |
| 17-16 | GCM | R/W | 0h | AES-GCM Mode Enable This is a combined mode, using the Galois field-multiplier GF(2128) for authentication and AES-CTR mode for encryption the bits specify the GCM mode. Value Description 0x0 No operation 0x1 GHASH with H loaded and Y0-encrypted forced to zero 0x2 GHASH with H loaded and Y0-encrypted calculated internally 0x3 Autonomous GHASH (both H and Y0-encrypted calculated internally) Reset type: PER.RESET |
| 15 | CBCMAC | R/W | 0h | AES-CBC MAC Enable The DIRECTION bit must be set to 1 for this mode. Value Description 0 AES-CBC MAC mode is not enabled. 1 AES-CBC MAC mode enabled. Reset type: PER.RESET |
| 14 | F9 | R/W | 0h | AES f9 Mode Enable The AES key size must be set to 128-bit for this mode. Value Description 0 f9 mode is not enabled 1 f9 mode is enabled. Reset type: PER.RESET |
| 13 | F8 | R/W | 0h | AES f8 Mode Enable, The KEY_SIZE must be set to 128-bit for this mode. Value Description 0 AES f8 mode is not enabled. 1 AES f8 mode is enabled. Reset type: PER.RESET |
| 12-11 | XTS | R/W | 0h | AES-XTS Operation Enable The bits specify the XTS mode. Value Description 0x0 No operation 0x1 Previous/intermediate tweak value and j loaded (value is loaded via IV, j is loaded via the AAD length register) 0x2 Key2, n and j are loaded (n is loaded via IV, j is loaded via the AAD length register) 0x3 Key2 and n are loaded j=0 (n is loaded via IV) Reset type: PER.RESET |
| 10 | CFB | R/W | 0h | Full block AES cipher feedback mode (CFB128) Enable Value Description 0 AES-CFB mode is not enabled. 1 AES-CFB mode is enabled. Reset type: PER.RESET |
| 9 | ICM | R/W | 0h | AES Integer Counter Mode (ICM) Enable This is a counter mode with a 16-bit wide counter. Value Description 0 AES-ICM mode is not enabled. 1 AES-ICM mode is enabled. Reset type: PER.RESET |
| 8-7 | CTR_WIDTH | R/W | 0h | AES-CTR Mode Counter Width Value Description 0x0 Counter is 32 bits 0x1 Counter is 64 bits 0x2 Counter is 96 bits 0x3 Counter is 128 bits Reset type: PER.RESET |
| 6 | CTR | R/W | 0h | Counter Mode This bit must also be set for GCM and CCM mode, when encryption/decryption is required. Value Description 0 Counter mode is not enabled. 1 Counter mode is enabled. Reset type: PER.RESET |
| 5 | MODE | R/W | 0h | ECB/CBC Mode Value Description 0 ECB mode 1 CBC mode Reset type: PER.RESET |
| 4-3 | KEY_SIZE | R/W | 0h | Key Size Value Description 0x0 reserved 0x1 Key is 128 bits 0x2 Key is 192 bits 0x3 Key is 256 bits Reset type: PER.RESET |
| 2 | DIRECTION | R/W | 0h | Encryption/Decryption Selection If set to =1, an encrypt operation is performed. If set to 0, a decrypt operation is performed. DIRECTION Value Description 0 Decryption is selected. 1 Encryption is selected. Reset type: PER.RESET |
| 1 | INPUT_READY | R | 0h | Input Ready Status Value Description 0 Input buffer is not empty. 1 Indicates that the 16-byte input buffer is empty, and the host is permitted to write the next block of data. Reset type: PER.RESET |
| 0 | OUTPUT_READY | R | 0h | Output Ready Status Value Description 0 No AES output block is available. 1 An AES output block is available for the host to retrieve. Reset type: PER.RESET |
AES_C_LENGTH_0 is shown in Figure 31-35 and described in Table 31-30.
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Secure Host Interface Bank LSW
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LENGTH | |||||||||||||||||||||||||||||||
| R-0/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | LENGTH | R-0/W | 0h | Bits [60:0] of the crypto length registers (LSW and MSW) store the cryptographic data length in bytes for all modes. Once processing with this context is started, this length decrements to zero. Data lengths up to (261 - 1) bytes are allowed. For GCM, any value up to 236 - 32 bytes can be used. This is because a 32-bit counter mode is used the maximum number of 128-bit blocks is 232 - 2, resulting in a maximum number of bytes of 236 - 32. A write to this register triggers the engine to start using this context. This is valid for all modes except GCM and CCM. Note that for the combined modes, this length does not include the authentication only data the authentication length is specified in the AES_AUTH_LENGTH register below. All modes must have a length > 0. For the combined modes, it is allowed to have one of the lengths equal to zero. For the basic encryption modes (ECB/CBC/CTR/ICM/CFB128) it is allowed to program zero to the length field in that case the length is assumed infinite. All data must be byte (8-bit) aligned for stream cipher modes bit aligned data streams are not supported by the AES Engine. For block cipher modes, the data length must be programmed in multiples of the block cipher size, 16 bytes. For a Host read operation, these registers return all-zeroes. Reset type: PER.RESET |
AES_C_LENGTH_1 is shown in Figure 31-36 and described in Table 31-31.
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Secure Host Interface Bank MSW
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LENGTH | |||||||||||||||||||||||||||||||
| R-0/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | LENGTH | R-0/W | 0h | Bits [60:0] of the crypto length registers (LSW and MSW) store the cryptographic data length in bytes for all modes. Once processing with this context is started, this length decrements to zero. Data lengths up to (261 - 1) bytes are allowed. For GCM, any value up to 236 - 32 bytes can be used. This is because a 32-bit counter mode is used the maximum number of 128-bit blocks is 232 - 2, resulting in a maximum number of bytes of 236 - 32. A write to this register triggers the engine to start using this context. This is valid for all modes except GCM and CCM. Note that for the combined modes, this length does not include the authentication only data the authentication length is specified in the AES_AUTH_LENGTH register below. All modes must have a length > 0. For the combined modes, it is allowed to have one of the lengths equal to zero. For the basic encryption modes (ECB/CBC/CTR/ICM/CFB128) it is allowed to program zero to the length field in that case the length is assumed infinite. All data must be byte (8-bit) aligned for stream cipher modes bit aligned data streams are not supported by the AES Engine. For block cipher modes, the data length must be programmed in multiples of the block cipher size, 16 bytes. For a Host read operation, these registers return all-zeroes. Reset type: PER.RESET |
AES_AUTH_LENGTH is shown in Figure 31-37 and described in Table 31-32.
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Secure Host Interface Bank
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| AUTH | |||||||||||||||||||||||||||||||
| R-0/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | AUTH | R-0/W | 0h | Bits [31:0] of the authentication length register store the authentication data length in bytes for combined modes only (GCM or CCM) Supported AAD-lengths for CCM are from 0 to (216 - 28) bytes. For GCM any value up to (232 - 1) bytes can be used. Once processing with this context is started, this length decrements to zero. A write to this register triggers the engine to start using this context for GCM and CCM. For XTS this register is optionally used to load 'j'. Loading of 'j' is only required if 'j' != 0. 'j' is a 28-bit value and must be written to bits [31-4] of this register. 'j' represents the sequential number of the 128-bit block inside the data unit. For the first block in a unit, this value is zero. It is not required to provide a 'j' for each new data block within a unit. Note that it is possible to start with a 'j' unequal to zero refer to Table 4 for more details. For a Host read operation, these registers return all-zeroes. Reset type: PER.RESET |
AES_DATA_IN_OUT_0 is shown in Figure 31-38 and described in Table 31-33.
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Secure Host Interface Bank
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DATA | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | DATA | R/W | 0h | The Data Input/Output Registers buffer the input/output data blocks to/from the AES Engine. Notice that the data input buffer (AES_DATA_IN_n) and data output buffer (AES_DATA_OUT_n) are mapped to the same address locations. Writes to these addresses load the Input Buffer while reads pull from the Output Buffer. Therefore, for write access, the data input buffer is written for read access, the data output buffer is read. The data input buffer must be written prior to starting an operation. The data output buffer contains valid data on completion of an operation. All writes from, and reads to, these registers are tracked independently per direction and HIB. Therefore, any 128-bit data block can be split over multiple 32-bit word transfers, which can be mixed with other transfers over the external interface. Reset type: PER.RESET |
AES_DATA_IN_OUT_1 is shown in Figure 31-39 and described in Table 31-34.
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Secure Host Interface Bank
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DATA | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | DATA | R/W | 0h | The Data Input/Output Registers buffer the input/output data blocks to/from the AES Engine. Notice that the data input buffer (AES_DATA_IN_n) and data output buffer (AES_DATA_OUT_n) are mapped to the same address locations. Writes to these addresses load the Input Buffer while reads pull from the Output Buffer. Therefore, for write access, the data input buffer is written for read access, the data output buffer is read. The data input buffer must be written prior to starting an operation. The data output buffer contains valid data on completion of an operation. All writes from, and reads to, these registers are tracked independently per direction and HIB. Therefore, any 128-bit data block can be split over multiple 32-bit word transfers, which can be mixed with other transfers over the external interface. Reset type: PER.RESET |
AES_DATA_IN_OUT_2 is shown in Figure 31-40 and described in Table 31-35.
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Secure Host Interface Bank
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DATA | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | DATA | R/W | 0h | The Data Input/Output Registers buffer the input/output data blocks to/from the AES Engine. Notice that the data input buffer (AES_DATA_IN_n) and data output buffer (AES_DATA_OUT_n) are mapped to the same address locations. Writes to these addresses load the Input Buffer while reads pull from the Output Buffer. Therefore, for write access, the data input buffer is written for read access, the data output buffer is read. The data input buffer must be written prior to starting an operation. The data output buffer contains valid data on completion of an operation. All writes from, and reads to, these registers are tracked independently per direction and HIB. Therefore, any 128-bit data block can be split over multiple 32-bit word transfers, which can be mixed with other transfers over the external interface. Reset type: PER.RESET |
AES_DATA_IN_OUT_3 is shown in Figure 31-41 and described in Table 31-36.
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Secure Host Interface Bank
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DATA | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | DATA | R/W | 0h | The Data Input/Output Registers buffer the input/output data blocks to/from the AES Engine. Notice that the data input buffer (AES_DATA_IN_n) and data output buffer (AES_DATA_OUT_n) are mapped to the same address locations. Writes to these addresses load the Input Buffer while reads pull from the Output Buffer. Therefore, for write access, the data input buffer is written for read access, the data output buffer is read. The data input buffer must be written prior to starting an operation. The data output buffer contains valid data on completion of an operation. All writes from, and reads to, these registers are tracked independently per direction and HIB. Therefore, any 128-bit data block can be split over multiple 32-bit word transfers, which can be mixed with other transfers over the external interface. Reset type: PER.RESET |
AES_TAG_OUT_0 is shown in Figure 31-42 and described in Table 31-37.
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Secure Host Interface Bank
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH | R | 0h | Bits [31:0] of the AES TAG registers store the authentication value for the combined and authentication only modes. For a Host read operation, these registers contain the last 128-bit TAG output of the AES Engine the TAG is available until the next context is written. This register will only contain valid data if the TAG is available, when the 'store_ready' bit from AES_CTRL register is set. During processing or for operations/modes that do not return a TAG, reads from this register returns data from the IV register. For operations that do return a TAG in the IV register (e.g. XTS), the IV register must be accessed directly. Reset type: PER.RESET |
AES_TAG_OUT_1 is shown in Figure 31-43 and described in Table 31-38.
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Secure Host Interface Bank
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH | R | 0h | Bits [31:0] of the AES TAG registers store the authentication value for the combined and authentication only modes. For a Host read operation, these registers contain the last 128-bit TAG output of the AES Engine the TAG is available until the next context is written. This register will only contain valid data if the TAG is available, when the 'store_ready' bit from AES_CTRL register is set. During processing or for operations/modes that do not return a TAG, reads from this register returns data from the IV register. For operations that do return a TAG in the IV register (e.g. XTS), the IV register must be accessed directly. Reset type: PER.RESET |
AES_TAG_OUT_2 is shown in Figure 31-44 and described in Table 31-39.
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Secure Host Interface Bank
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH | R | 0h | Bits [31:0] of the AES TAG registers store the authentication value for the combined and authentication only modes. For a Host read operation, these registers contain the last 128-bit TAG output of the AES Engine the TAG is available until the next context is written. This register will only contain valid data if the TAG is available, when the 'store_ready' bit from AES_CTRL register is set. During processing or for operations/modes that do not return a TAG, reads from this register returns data from the IV register. For operations that do return a TAG in the IV register (e.g. XTS), the IV register must be accessed directly. Reset type: PER.RESET |
AES_TAG_OUT_3 is shown in Figure 31-45 and described in Table 31-40.
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Secure Host Interface Bank
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HASH | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | HASH | R | 0h | Bits [31:0] of the AES TAG registers store the authentication value for the combined and authentication only modes. For a Host read operation, these registers contain the last 128-bit TAG output of the AES Engine the TAG is available until the next context is written. This register will only contain valid data if the TAG is available, when the 'store_ready' bit from AES_CTRL register is set. During processing or for operations/modes that do not return a TAG, reads from this register returns data from the IV register. For operations that do return a TAG in the IV register (e.g. XTS), the IV register must be accessed directly. Reset type: PER.RESET |
AES_REV is shown in Figure 31-46 and described in Table 31-41.
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Secure Host Interface Bank
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| REVISION | |||||||||||||||||||||||||||||||
| R-40000B02h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | REVISION | R | 40000B02h | Revision number: 31-30:SCHEME = 0b01 29-28:Reserved=0b00 27-16:FUNC = 0x000 15-11:RTL Revision = 0b00001 10-8:MAJOR = 0b011 7-2:CUSTOM = 0b000000 1-0:MINOR = 0b10 Reset type: PER.RESET |
AES_SYSCONFIG is shown in Figure 31-47 and described in Table 31-42.
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Secure Host Interface Bank
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | RESERVED | RESERVED | RESERVED | MAP_CONTEXT_OUT_ON_DATA_OUT | DMA_REQ_CONTEXT_OUT_EN | ||
| R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DMA_REQ_CONTEXT_IN_EN | DMA_REQ_DATA_OUT_EN | DMA_REQ_DATA_IN_EN | RESERVED | SIDLE | SOFTRESET | AUTOIDLE | |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-1h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-13 | RESERVED | R | 0h | Reserved |
| 12 | RESERVED | R/W | 0h | Reserved |
| 11 | RESERVED | R/W | 0h | Reserved |
| 10 | RESERVED | R/W | 0h | Reserved |
| 9 | MAP_CONTEXT_OUT_ON_DATA_OUT | R/W | 0h | If set to '1' the two context out requests (dma_req_context_out_en, Bit [8] above, and context_out interrupt enable, Bit [3] of AES_IRQENABLE register) are mapped on the corresponding data output request bit. In this case, the original 'context out' bit values are ignored. Therefore, when this bit is enabled and the dma_req_data_out_en (Bit [6]) is enabled, this DMA request is used for the context output and data output. Similarly if the data_out interrupt enable (Bit [2] of AES_IRQENABLE register) is enabled, this interrupt is used for context output and data output. Note that when context and data output request or interrupt are mapped on each other, the context output is always requested after the last data output. Reset type: PER.RESET |
| 8 | DMA_REQ_CONTEXT_OUT_EN | R/W | 0h | DMA Request Context Out Enable If set to 1, the DMA context output request is enabled (for context data out, for example, TAG for authentication modes). Value Description 0 DMA disabled for context output request. 1 DMA enabled for context output request. Reset type: PER.RESET |
| 7 | DMA_REQ_CONTEXT_IN_EN | R/W | 0h | DMA Request Context In Enable Value Description 0 DMA disabled for context input request. 1 DMA enabled for context input request. Reset type: PER.RESET |
| 6 | DMA_REQ_DATA_OUT_EN | R/W | 0h | DMA Request Data Out Enable Value Description 0 DMA disabled for data output request. 1 DMA enabled for data output request. Reset type: PER.RESET |
| 5 | DMA_REQ_DATA_IN_EN | R/W | 0h | DMA Request Data In Enable Value Description 0 DMA disabled for data input request. 1 DMA enabled for data input request. Reset type: PER.RESET |
| 4 | RESERVED | R/W | 0h | Reserved |
| 3-2 | SIDLE | R/W | 0h | Slave Idle Mode Value Description 0x0 Force-idle mode 0x1 No-idle 0x2 Smart-idle 0x3 reserved Reset type: PER.RESET |
| 1 | SOFTRESET | R/W | 0h | Soft reset Value Description 0 No operation 1 Start soft reset sequence Reset type: PER.RESET |
| 0 | AUTOIDLE | R/W | 1h | If set to 1, the internal clocks are switched off when there is no processing to be done. This bit is only available on the sHIB. Reset type: PER.RESET |
AES_SYSSTATUS is shown in Figure 31-48 and described in Table 31-43.
Return to the Summary Table.
Secure Host Interface Bank
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RESETDONE | ||||||
| R-0h | R-1h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-1 | RESERVED | R | 0h | Reserved |
| 0 | RESETDONE | R | 1h | Reset Done Value Description 0 Reset is not complete. 1 Reset is has completed. Reset type: PER.RESET |
AES_IRQSTATUS is shown in Figure 31-49 and described in Table 31-44.
Return to the Summary Table.
Secure Host Interface Bank
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CONTEXT_OUT | DATA_OUT | DATA_IN | CONTEXT_IN | |||
| R-0h | R-0h | R-0h | R-0h | R-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-4 | RESERVED | R | 0h | Reserved |
| 3 | CONTEXT_OUT | R | 0h | Context Output Interrupt Status Value Description 0 Authentication tag (and IV) interrupt(s) is/are not active. 1 Authentication tag (and IV) interrupt(s) is/are active and the interrupt output has been triggered. Reset type: PER.RESET |
| 2 | DATA_OUT | R | 0h | Data Out Interrupt Status Value Description 0 The data out interrupt is not active. 1 The data out interrupt is active and the interrupt output has been triggered. Reset type: PER.RESET |
| 1 | DATA_IN | R | 0h | Data In Interrupt Status Value Description 0 The data in interrupt is not active. 1 The data in interrupt is active and the interrupt output has been triggered. Reset type: PER.RESET |
| 0 | CONTEXT_IN | R | 0h | Context In Interrupt Status Value Description 0 The context in interrupt is not active. 1 The context in interrupt is active and the interrupt output has been triggered. Reset type: PER.RESET |
AES_IRQENABLE is shown in Figure 31-50 and described in Table 31-45.
Return to the Summary Table.
Secure Host Interface Bank
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CONTEXT_OUT | DATA_OUT | DATA_IN | CONTEXT_IN | |||
| R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-4 | RESERVED | R | 0h | Reserved |
| 3 | CONTEXT_OUT | R/W | 0h | Context Out Interrupt Enable Value Description 0 Authentication tag (and IV) interrupt(s) is/are disabled. 1 Authentication tag (and IV) interrupt(s) is/are enabled. Reset type: PER.RESET |
| 2 | DATA_OUT | R/W | 0h | Data Out Interrupt Enable Value Description 0 The data out interrupt is disabled. 1 The data out interrupt is enabled. Reset type: PER.RESET |
| 1 | DATA_IN | R/W | 0h | Data In Interrupt Enable Value Description 0 The data in interrupt is disabled. 1 The data in interrupt is enabled. Reset type: PER.RESET |
| 0 | CONTEXT_IN | R/W | 0h | Context In Interrupt Enable Value Description 0 The context in interrupt is disabled. 1 The context in interrupt is enabled. Reset type: PER.RESET |
AES_DIRTY_BITS is shown in Figure 31-51 and described in Table 31-46.
Return to the Summary Table.
Secure Host Interface Bank
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RESERVED | RESERVED | S_DIRTY | S_ACCESS | |||
| R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-4 | RESERVED | R | 0h | Reserved |
| 3 | RESERVED | R/W1S | 0h | Reserved |
| 2 | RESERVED | R/W1S | 0h | Reserved |
| 1 | S_DIRTY | R/W1S | 0h | AES Dirty Bit This bit must be written to a 1 to clear. Value Description 0 No AES registers have been written. 1 Indicates when any of the AES_x registers have been written (except for the AES_DIRTYBITS register). Reset type: PER.RESET |
| 0 | S_ACCESS | R/W1S | 0h | AES Access Bit This bit must be written to a 1 to clear. Value Description 0 No AES registers have been read. 1 Indicates when any of the AES_x registers have been read (except for the AES_DIRTYBITS register). Reset type: PER.RESET |