SPRUJ53B
April 2024 – September 2024
TMS320F28P550SJ
,
TMS320F28P559SJ-Q1
1
Read This First
About This Manual
Notational Conventions
Glossary
Related Documentation From Texas Instruments
Support Resources
Trademarks
1
C2000™ Microcontrollers Software Support
1.1
Introduction
1.2
C2000Ware Structure
1.3
Documentation
1.4
Devices
1.5
Libraries
1.6
Code Composer Studio™ Integrated Development Environment (IDE)
1.7
SysConfig and PinMUX Tool
2
C28x Processor
2.1
Introduction
2.2
C28X Related Collateral
2.3
Features
2.4
Floating-Point Unit (FPU)
2.5
Trigonometric Math Unit (TMU)
2.6
VCRC Unit
3
System Control and Interrupts
3.1
Introduction
3.1.1
SYSCTL Related Collateral
3.1.2
LOCK Protection on System Configuration Registers
3.1.3
EALLOW Protection
3.2
Power Management
3.3
Device Identification and Configuration Registers
3.4
Resets
3.4.1
Reset Sources
3.4.2
External Reset (XRS)
3.4.3
Simulate External Reset (SIMRESET.XRS)
3.4.4
Power-On Reset (POR)
3.4.5
Brown-Out Reset (BOR)
3.4.6
Debugger Reset (SYSRS)
3.4.7
Simulate CPU Reset (SIMRESET)
3.4.8
Watchdog Reset (WDRS)
3.4.9
NMI Watchdog Reset (NMIWDRS)
3.4.10
DCSM Safe Code Copy Reset (SCCRESET)
3.5
Peripheral Interrupts
3.5.1
Interrupt Concepts
3.5.2
Interrupt Architecture
3.5.2.1
Peripheral Stage
3.5.2.2
PIE Stage
3.5.2.3
CPU Stage
3.5.3
Interrupt Entry Sequence
3.5.4
Configuring and Using Interrupts
3.5.4.1
Enabling Interrupts
3.5.4.2
Handling Interrupts
3.5.4.3
Disabling Interrupts
3.5.4.4
Nesting Interrupts
3.5.4.5
Vector Address Validity Check
3.5.5
PIE Channel Mapping
3.5.6
PIE Interrupt Priority
3.5.6.1
Channel Priority
3.5.6.2
Group Priority
3.5.7
System Error
3.5.8
Vector Tables
3.6
Exceptions and Non-Maskable Interrupts
3.6.1
Configuring and Using NMIs
3.6.2
Emulation Considerations
3.6.3
NMI Sources
3.6.3.1
Missing Clock Detection
3.6.3.2
RAM Uncorrectable Error
3.6.3.3
Flash Uncorrectable ECC Error
3.6.3.4
Software-Forced Error
3.6.3.5
ERAD NMI
3.6.4
Illegal Instruction Trap (ITRAP)
3.6.5
ERRORSTS Pin
3.7
Clocking
3.7.1
Clock Sources
3.7.1.1
Primary Internal Oscillator (INTOSC2)
3.7.1.2
Backup Internal Oscillator (INTOSC1)
3.7.1.3
Auxiliary Clock Input (AUXCLKIN)
3.7.1.4
External Oscillator (XTAL)
3.7.2
Derived Clocks
3.7.2.1
Oscillator Clock (OSCCLK)
3.7.2.2
System PLL Output Clock (PLLRAWCLK)
3.7.3
Device Clock Domains
3.7.3.1
System Clock (PLLSYSCLK)
3.7.3.2
CPU Clock (CPUCLK)
3.7.3.3
CPU Subsystem Clock (SYSCLK and PERx.SYSCLK)
3.7.3.4
Low-Speed Peripheral Clock (LSPCLK and PERx.LSPCLK)
3.7.3.5
USB Bit Clock
3.7.3.6
CAN Bit Clock
3.7.3.7
CLB Clock
3.7.3.8
LIN Clock
3.7.3.9
CPU Timer2 Clock (TIMER2CLK)
3.7.4
XCLKOUT
3.7.5
Clock Connectivity
3.7.6
Clock Source and PLL Setup
3.7.7
Using an External Crystal or Resonator
3.7.7.1
X1/X2 Precondition Circuit
3.7.8
Using an External Oscillator
3.7.9
Choosing PLL Settings
3.7.10
System Clock Setup
3.7.11
SYS PLL Bypass
3.7.12
Clock (OSCCLK) Failure Detection
3.7.12.1
Missing Clock Detection
3.8
32-Bit CPU Timers 0/1/2
3.9
Watchdog Timer
3.9.1
Servicing the Watchdog Timer
3.9.2
Minimum Window Check
3.9.3
Watchdog Reset or Watchdog Interrupt Mode
3.9.4
Watchdog Operation in Low-Power Modes
3.9.5
Emulation Considerations
3.10
Low-Power Modes
3.10.1
Clock-Gating Low-Power Modes
3.10.2
IDLE
3.10.3
STANDBY
3.10.4
HALT
3.11
Memory Controller Module
3.11.1
Functional Description
3.11.1.1
Dedicated RAM (Mx RAM)
3.11.1.2
Local Shared RAM (LSx RAM)
3.11.1.3
Global Shared RAM (GSx RAM)
3.11.1.4
CAN Message RAM
3.11.1.5
CLA-CPU Message RAM
3.11.1.6
CLA-DMA Message RAM
3.11.1.7
Access Arbitration
3.11.1.8
Access Protection
3.11.1.8.1
CPU Fetch Protection
3.11.1.8.2
CPU Write Protection
3.11.1.8.3
CPU Read Protection
3.11.1.8.4
CLA Fetch Protection
3.11.1.8.5
CLA Write Protection
3.11.1.8.6
CLA Read Protection
3.11.1.8.7
DMA Write Protection
3.11.1.8.8
NPU Write Protection
3.11.1.9
Memory Error Detection, Correction, and Error Handling
3.11.1.9.1
Error Detection and Correction
3.11.1.9.2
Error Handling
3.11.1.10
Application Test Hooks for Error Detection and Correction
3.11.1.11
RAM Initialization
3.12
JTAG
3.12.1
JTAG Noise and TAP_STATUS
3.13
Live Firmware Update
3.13.1
LFU Background
3.13.2
LFU Switchover Steps
3.13.3
Device Features Supporting LFU
3.13.3.1
Multi-Bank Flash
3.13.3.2
PIE Vector Table Swap
3.13.3.3
LS0/LS1 RAM Memory Swap
3.13.3.3.1
Applicability to CLA LFU
3.13.4
LFU Switchover
3.13.5
LFU Resources
3.14
System Control Register Configuration Restrictions
3.15
Software
3.15.1
SYSCTL Registers to Driverlib Functions
3.15.2
CPUTIMER Registers to Driverlib Functions
3.15.3
MEMCFG Registers to Driverlib Functions
3.15.4
PIE Registers to Driverlib Functions
3.15.5
NMI Registers to Driverlib Functions
3.15.6
XINT Registers to Driverlib Functions
3.15.7
WWD Registers to Driverlib Functions
3.15.8
SYSCTL Examples
3.15.8.1
Missing clock detection (MCD)
3.15.8.2
XCLKOUT (External Clock Output) Configuration
3.15.9
TIMER Examples
3.15.9.1
CPU Timers
3.15.9.2
CPU Timers
3.15.10
MEMCFG Examples
3.15.10.1
Correctable & Uncorrectable Memory Error Handling
3.15.11
INTERRUPT Examples
3.15.11.1
External Interrupts (ExternalInterrupt)
3.15.11.2
Multiple interrupt handling of I2C, SCI & SPI Digital Loopback
3.15.11.3
CPU Timer Interrupt Software Prioritization
3.15.11.4
EPWM Real-Time Interrupt
3.15.12
LPM Examples
3.15.12.1
Low Power Modes: Device Idle Mode and Wakeup using GPIO
3.15.12.2
Low Power Modes: Device Idle Mode and Wakeup using Watchdog
3.15.12.3
Low Power Modes: Device Standby Mode and Wakeup using GPIO
3.15.12.4
Low Power Modes: Device Standby Mode and Wakeup using Watchdog
3.15.12.5
Low Power Modes: Halt Mode and Wakeup using GPIO
3.15.12.6
Low Power Modes: Halt Mode and Wakeup
3.15.13
WATCHDOG Examples
3.15.13.1
Watchdog
3.16
SYSCTRL Registers
3.16.1
SYSCTRL Base Address Table
3.16.2
CPUTIMER_REGS Registers
3.16.3
PIE_CTRL_REGS Registers
3.16.4
NMI_INTRUPT_REGS Registers
3.16.5
XINT_REGS Registers
3.16.6
SYNC_SOC_REGS Registers
3.16.7
DMA_CLA_SRC_SEL_REGS Registers
3.16.8
LFU_REGS Registers
3.16.9
DEV_CFG_REGS Registers
3.16.10
CLK_CFG_REGS Registers
3.16.11
CPU_SYS_REGS Registers
3.16.12
SYS_STATUS_REGS Registers
3.16.13
PERIPH_AC_REGS Registers
3.16.14
MEM_CFG_REGS Registers
3.16.15
ACCESS_PROTECTION_REGS Registers
3.16.16
MEMORY_ERROR_REGS Registers
3.16.17
TEST_ERROR_REGS Registers
3.16.18
UID_REGS Registers
4
ROM Code and Peripheral Booting
4.1
Introduction
4.1.1
ROM Related Collateral
4.2
Device Boot Sequence
4.3
Device Boot Modes
4.3.1
Default Boot Modes
4.3.2
Custom Boot Modes
4.4
Device Boot Configurations
4.4.1
Configuring Boot Mode Pins
4.4.2
Configuring Boot Mode Table Options
4.4.3
Boot Mode Example Use Cases
4.4.3.1
Zero Boot Mode Select Pins
4.4.3.2
One Boot Mode Select Pin
4.4.3.3
Three Boot Mode Select Pins
4.5
Device Boot Flow Diagrams
4.5.1
Boot Flow
4.5.2
Emulation Boot Flow
4.5.3
Standalone Boot Flow
4.6
Device Reset and Exception Handling
4.6.1
Reset Causes and Handling
4.6.2
Exceptions and Interrupts Handling
4.7
Boot ROM Description
4.7.1
Boot ROM Configuration Registers
4.7.1.1
Flash Write Protection
4.7.1.2
MPOST Configuration
4.7.2
Entry Points
4.7.3
Wait Points
4.7.4
Secure Flash Boot
4.7.4.1
Secure Flash CPU1 Linker File Example
4.7.5
Firmware Update (FWU) Flash Boot
4.7.6
Memory Maps
4.7.6.1
Boot ROM Memory Maps
4.7.6.2
CLA Data ROM Memory Maps
4.7.6.3
Reserved RAM Memory Maps
4.7.7
ROM Tables
4.7.8
Boot Modes and Loaders
4.7.8.1
Boot Modes
4.7.8.1.1
Flash Boot
4.7.8.1.2
RAM Boot
4.7.8.1.3
Wait Boot
4.7.8.2
Bootloaders
4.7.8.2.1
SCI Boot Mode
4.7.8.2.2
SPI Boot Mode
4.7.8.2.3
I2C Boot Mode
4.7.8.2.4
Parallel Boot Mode
4.7.8.2.5
CAN Boot Mode (MCAN in non-FD mode)
4.7.8.2.6
CAN-FD Boot Mode
4.7.8.2.7
USB Boot Mode
4.7.9
GPIO Assignments
4.7.10
Secure ROM Function APIs
4.7.11
Clock Initializations
4.7.12
Boot Status Information
4.7.12.1
Booting Status
4.7.12.2
Boot Mode and MPOST (Memory Power On Self-Test) Status
4.7.13
ROM Version
4.8
Application Notes for Using the Bootloaders
4.8.1
Bootloader Data Stream Structure
4.8.1.1
Data Stream Structure 8-bit
4.8.2
The C2000 Hex Utility
4.8.2.1
HEX2000.exe Command Syntax
4.9
Software
4.9.1
BOOT Examples
5
Dual Code Security Module (DCSM)
5.1
Introduction
5.1.1
DCSM Related Collateral
5.2
Functional Description
5.2.1
CSM Passwords
5.2.2
Emulation Code Security Logic (ECSL)
5.2.3
CPU Secure Logic
5.2.4
Execute-Only Protection
5.2.5
Password Lock
5.2.6
JTAGLOCK
5.2.7
Link Pointer and Zone Select
5.2.8
C Code Example to Get Zone Select Block Addr for Zone1
5.3
Flash and OTP Erase/Program
5.4
Secure Copy Code
5.5
SecureCRC
5.6
CSM Impact on Other On-Chip Resources
5.7
Incorporating Code Security in User Applications
5.7.1
Environments That Require Security Unlocking
5.7.2
CSM Password Match Flow
5.7.3
C Code Example to Unsecure C28x Zone1
5.7.4
C Code Example to Resecure C28x Zone1
5.7.5
Environments That Require ECSL Unlocking
5.7.6
ECSL Password Match Flow
5.7.7
ECSL Disable Considerations for any Zone
5.7.7.1
C Code Example to Disable ECSL for C28x Zone1
5.7.8
Device Unique ID
5.8
Software
5.8.1
DCSM Registers to Driverlib Functions
5.8.2
DCSM Examples
5.8.2.1
Empty DCSM Tool Example
5.9
DCSM Registers
5.9.1
DCSM Base Address Table
5.9.2
DCSM_Z1_REGS Registers
5.9.3
DCSM_Z2_REGS Registers
5.9.4
DCSM_COMMON_REGS Registers
5.9.5
DCSM_Z1_OTP Registers
5.9.6
DCSM_Z2_OTP Registers
6
Flash Module
6.1
Introduction to Flash and OTP Memory
6.1.1
FLASH Related Collateral
6.1.2
Features
6.1.3
Flash Tools
6.1.4
Default Flash Configuration
6.2
Flash Bank, OTP, and Pump
6.3
Flash Wrapper
6.4
Flash and OTP Memory Performance
6.5
Flash Read Interface
6.5.1
C28x-Flash Read Interface
6.5.1.1
Standard Read Mode
6.5.1.2
Prefetch Mode
6.5.1.3
Data Cache
6.5.1.4
Flash Read Operation
6.6
Flash Erase and Program
6.6.1
Erase
6.6.2
Program
6.6.3
Verify
6.7
Error Correction Code (ECC) Protection
6.7.1
Single-Bit Data Error
6.7.2
Uncorrectable Error
6.7.3
Mechanism to Check the Correctness of ECC Logic
6.8
Reserved Locations Within Flash and OTP
6.9
Migrating an Application from RAM to Flash
6.10
Procedure to Change the Flash Control Registers
6.11
Software
6.11.1
FLASH Registers to Driverlib Functions
6.11.2
FLASH Examples
6.11.2.1
Flash Programming with AutoECC, DataAndECC, DataOnly and EccOnly
6.11.2.2
Flash Programming with AutoECC, DataAndECC, DataOnly and EccOnly
6.12
FLASH Registers
6.12.1
FLASH Base Address Table
6.12.2
FLASH_CTRL_REGS Registers
6.12.3
FLASH_ECC_REGS Registers
7
Control Law Accelerator (CLA)
7.1
Introduction
7.1.1
Features
7.1.2
CLA Related Collateral
7.1.3
Block Diagram
7.2
CLA Interface
7.2.1
CLA Memory
7.2.2
CLA Memory Bus
7.2.3
Shared Peripherals and EALLOW Protection
7.2.4
CLA Tasks and Interrupt Vectors
7.3
CLA, DMA, and CPU Arbitration
7.3.1
CLA Message RAM
7.3.2
CLA Program Memory
7.3.3
CLA Data Memory
7.3.4
Peripheral Registers (ePWM, HRPWM, Comparator)
7.4
CLA Configuration and Debug
7.4.1
Building a CLA Application
7.4.2
Typical CLA Initialization Sequence
7.4.3
Debugging CLA Code
7.4.3.1
Breakpoint Support (MDEBUGSTOP)
7.4.4
CLA Illegal Opcode Behavior
7.4.5
Resetting the CLA
7.5
Pipeline
7.5.1
Pipeline Overview
7.5.2
CLA Pipeline Alignment
7.5.2.1
Code Fragment For MBCNDD, MCCNDD, or MRCNDD
359
7.5.2.2
Code Fragment for Loading MAR0 or MAR1
361
7.5.2.3
ADC Early Interrupt to CLA Response
7.5.3
Parallel Instructions
7.5.3.1
Math Operation with Parallel Load
7.5.3.2
Multiply with Parallel Add
7.5.4
CLA Task Execution Latency
7.6
Software
7.6.1
CLA Registers to Driverlib Functions
7.6.2
CLA Examples
7.6.2.1
CLA arcsine(x) using a lookup table (cla_asin_cpu01)
7.6.2.2
CLA arcsine(x) using a lookup table (cla_asin_cpu01)
7.6.2.3
CLA arctangent(x) using a lookup table (cla_atan_cpu01)
7.6.2.4
CLA background nesting task
7.6.2.5
Controlling PWM output using CLA
7.6.2.6
Just-in-time ADC sampling with CLA
7.6.2.7
Optimal offloading of control algorithms to CLA
7.6.2.8
Handling shared resources across C28x and CLA
7.7
Instruction Set
7.7.1
Instruction Descriptions
7.7.2
Addressing Modes and Encoding
7.7.3
Instructions
MABSF32 MRa, MRb
MADD32 MRa, MRb, MRc
MADDF32 MRa, #16FHi, MRb
MADDF32 MRa, MRb, #16FHi
MADDF32 MRa, MRb, MRc
MADDF32 MRd, MRe, MRf||MMOV32 mem32, MRa
MADDF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
MAND32 MRa, MRb, MRc
MASR32 MRa, #SHIFT
MBCNDD 16BitDest [, CNDF]
MCCNDD 16BitDest [, CNDF]
MCMP32 MRa, MRb
MCMPF32 MRa, MRb
MCMPF32 MRa, #16FHi
MDEBUGSTOP
MEALLOW
MEDIS
MEINVF32 MRa, MRb
MEISQRTF32 MRa, MRb
MF32TOI16 MRa, MRb
MF32TOI16R MRa, MRb
MF32TOI32 MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MF32TOUI32 MRa, MRb
MFRACF32 MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MI32TOF32 MRa, mem32
MI32TOF32 MRa, MRb
MLSL32 MRa, #SHIFT
MLSR32 MRa, #SHIFT
MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32
MMAXF32 MRa, MRb
MMAXF32 MRa, #16FHi
MMINF32 MRa, MRb
MMINF32 MRa, #16FHi
MMOV16 MARx, MRa, #16I
MMOV16 MARx, mem16
MMOV16 mem16, MARx
MMOV16 mem16, MRa
MMOV32 mem32, MRa
MMOV32 mem32, MSTF
MMOV32 MRa, mem32 [, CNDF]
MMOV32 MRa, MRb [, CNDF]
MMOV32 MSTF, mem32
MMOVD32 MRa, mem32
MMOVF32 MRa, #32F
MMOVI16 MARx, #16I
MMOVI32 MRa, #32FHex
MMOVIZ MRa, #16FHi
MMOVZ16 MRa, mem16
MMOVXI MRa, #16FLoHex
MMPYF32 MRa, MRb, MRc
MMPYF32 MRa, #16FHi, MRb
MMPYF32 MRa, MRb, #16FHi
MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf
MMPYF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
MMPYF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc ||MSUBF32 MRd, MRe, MRf
MNEGF32 MRa, MRb[, CNDF]
MNOP
MOR32 MRa, MRb, MRc
MRCNDD [CNDF]
MSETFLG FLAG, VALUE
MSTOP
MSUB32 MRa, MRb, MRc
MSUBF32 MRa, MRb, MRc
MSUBF32 MRa, #16FHi, MRb
MSUBF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
MSUBF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
MSWAPF MRa, MRb [, CNDF]
MTESTTF CNDF
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb
MUI32TOF32 MRa, mem32
MUI32TOF32 MRa, MRb
MXOR32 MRa, MRb, MRc
7.8
CLA Registers
7.8.1
CLA Base Address Table
7.8.2
CLA_ONLY_REGS Registers
7.8.3
CLA_SOFTINT_REGS Registers
7.8.4
CLA_REGS Registers
8
Neural-network Processing Unit (NPU)
8.1
Introduction
8.1.1
NPU Related Collateral
9
Dual-Clock Comparator (DCC)
9.1
Introduction
9.1.1
Features
9.1.2
Block Diagram
9.2
Module Operation
9.2.1
Configuring DCC Counters
9.2.2
Single-Shot Measurement Mode
9.2.3
Continuous Monitoring Mode
9.2.4
Error Conditions
9.3
Interrupts
9.4
Software
9.4.1
DCC Registers to Driverlib Functions
9.4.2
DCC Examples
9.4.2.1
DCC Single shot Clock measurement
9.4.2.2
DCC Single shot Clock verification
9.4.2.3
DCC Continuous clock monitoring
9.4.2.4
DCC Continuous clock monitoring
9.4.2.5
DCC Detection of clock failure
9.5
DCC Registers
9.5.1
DCC Base Address Table
9.5.2
DCC_REGS Registers
10
General-Purpose Input/Output (GPIO)
10.1
Introduction
10.1.1
GPIO Related Collateral
10.2
Configuration Overview
10.3
Digital Inputs on ADC Pins (AIOs)
10.4
Digital Inputs and Outputs on ADC Pins (AGPIOs)
10.5
Digital General-Purpose I/O Control
10.6
Input Qualification
10.6.1
No Synchronization (Asynchronous Input)
10.6.2
Synchronization to SYSCLKOUT Only
10.6.3
Qualification Using a Sampling Window
10.7
USB Signals
10.8
PMBUS and I2C Signals
10.9
GPIO and Peripheral Muxing
10.9.1
GPIO Muxing
10.9.2
Peripheral Muxing
10.10
Internal Pullup Configuration Requirements
10.11
Software
10.11.1
GPIO Registers to Driverlib Functions
10.11.2
GPIO Examples
10.11.2.1
Device GPIO Setup
10.11.2.2
Device GPIO Toggle
10.11.2.3
Device GPIO Interrupt
10.11.2.4
External Interrupt (XINT)
10.11.3
LED Examples
10.12
GPIO Registers
10.12.1
GPIO Base Address Table
10.12.2
GPIO_CTRL_REGS Registers
10.12.3
GPIO_DATA_REGS Registers
10.12.4
GPIO_DATA_READ_REGS Registers
11
Crossbar (X-BAR)
11.1
Input X-BAR and CLB Input X-BAR
11.1.1
CLB Input X-BAR
11.2
ePWM , CLB, and GPIO Output X-BAR
11.2.1
ePWM X-BAR
11.2.1.1
ePWM X-BAR Architecture
11.2.2
CLB X-BAR
11.2.2.1
CLB X-BAR Architecture
11.2.3
GPIO Output X-BAR
11.2.3.1
GPIO Output X-BAR Architecture
11.2.4
X-BAR Flags
11.3
Software
11.3.1
INPUTXBAR Registers to Driverlib Functions
11.3.2
EPWMXBAR Registers to Driverlib Functions
11.3.3
CLBXBAR Registers to Driverlib Functions
11.3.4
OUTPUTXBAR Registers to Driverlib Functions
11.3.5
XBAR Registers to Driverlib Functions
11.4
XBAR Registers
11.4.1
XBAR Base Address Table
11.4.2
INPUT_XBAR_REGS Registers
11.4.3
XBAR_REGS Registers
11.4.4
EPWM_XBAR_REGS Registers
11.4.5
CLB_XBAR_REGS Registers
11.4.6
OUTPUT_XBAR_REGS Registers
11.4.7
OUTPUT_XBAR_REGS Registers
12
Direct Memory Access (DMA)
12.1
Introduction
12.1.1
Features
12.1.2
Block Diagram
12.2
Architecture
12.2.1
Peripheral Interrupt Event Trigger Sources
12.2.2
DMA Bus
12.3
Address Pointer and Transfer Control
12.4
Pipeline Timing and Throughput
12.5
CPU and CLA Arbitration
12.6
Channel Priority
12.6.1
Round-Robin Mode
12.6.2
Channel 1 High-Priority Mode
12.7
Overrun Detection Feature
12.8
Software
12.8.1
DMA Registers to Driverlib Functions
12.8.2
DMA Examples
12.8.2.1
DMA GSRAM Transfer (dma_ex1_gsram_transfer)
12.8.2.2
DMA GSRAM Transfer (dma_ex2_gsram_transfer)
12.9
DMA Registers
12.9.1
DMA Base Address Table
12.9.2
DMA_REGS Registers
12.9.3
DMA_CH_REGS Registers
13
Embedded Real-time Analysis and Diagnostic (ERAD)
13.1
Introduction
13.1.1
ERAD Related Collateral
13.2
Enhanced Bus Comparator Unit
13.2.1
Enhanced Bus Comparator Unit Operations
13.2.2
Event Masking and Exporting
13.3
System Event Counter Unit
13.3.1
System Event Counter Modes
13.3.1.1
Counting Active Levels Versus Edges
13.3.1.2
Max Mode
13.3.1.3
Cumulative Mode
13.3.1.4
Input Signal Selection
13.3.2
Reset on Event
13.3.3
Operation Conditions
13.4
ERAD Ownership, Initialization and Reset
13.5
ERAD Programming Sequence
13.5.1
Hardware Breakpoint and Hardware Watch Point Programming Sequence
13.5.2
Timer and Counter Programming Sequence
13.6
Cyclic Redundancy Check Unit
13.6.1
CRC Unit Qualifier
13.6.2
CRC Unit Programming Sequence
13.7
Program Counter Trace
13.7.1
Functional Block Diagram
13.7.2
Trace Qualification Modes
13.7.2.1
Trace Qualifier Input Signals
13.7.3
Trace Memory
13.7.4
Trace Input Signal Conditioning
13.7.5
PC Trace Software Operation
13.7.6
Trace Operation in Debug Mode
13.8
Software
13.8.1
ERAD Registers to Driverlib Functions
13.8.2
ERAD Examples
13.8.2.1
ERAD Profiling Interrupts
13.8.2.2
ERAD Profile Function
13.8.2.3
ERAD Profile Function
13.8.2.4
ERAD HWBP Monitor Program Counter
13.8.2.5
ERAD HWBP Monitor Program Counter
13.8.2.6
ERAD Profile Function
13.8.2.7
ERAD HWBP Stack Overflow Detection
13.8.2.8
ERAD HWBP Stack Overflow Detection
13.8.2.9
ERAD Stack Overflow
13.8.2.10
ERAD Profile Interrupts CLA
13.8.2.11
ERAD Profiling Interrupts
13.8.2.12
ERAD Profiling Interrupts
13.8.2.13
ERAD MEMORY ACCESS RESTRICT
13.8.2.14
ERAD INTERRUPT ORDER
13.8.2.15
ERAD AND CLB
13.8.2.16
ERAD PWM PROTECTION
13.9
ERAD Registers
13.9.1
ERAD Base Address Table
13.9.2
ERAD_GLOBAL_REGS Registers
13.9.3
ERAD_HWBP_REGS Registers
13.9.4
ERAD_COUNTER_REGS Registers
13.9.5
ERAD_CRC_GLOBAL_REGS Registers
13.9.6
ERAD_CRC_REGS Registers
13.9.7
PCTRACE_REGS Registers
13.9.8
PCTRACE_BUFFER_REGS Registers
14
Analog Subsystem
14.1
Introduction
14.1.1
Features
14.1.2
Block Diagram
14.2
Optimizing Power-Up Time
14.3
Digital Inputs on ADC Pins (AIOs)
14.4
Digital Inputs and Outputs on ADC Pins (AGPIOs)
14.5
Analog Pins and Internal Connections
14.6
Software
14.6.1
ASYSCTL Registers to Driverlib Functions
14.7
ASBSYS Registers
14.7.1
ASBSYS Base Address Table
14.7.2
ANALOG_SUBSYS_REGS Registers
15
Analog-to-Digital Converter (ADC)
15.1
Introduction
15.1.1
ADC Related Collateral
15.1.2
Features
15.1.3
Block Diagram
15.2
ADC Configurability
15.2.1
Clock Configuration
15.2.2
Resolution
15.2.3
Voltage Reference
15.2.3.1
External Reference Mode
15.2.3.2
Internal Reference Mode
15.2.3.3
Ganged References
15.2.3.4
Selecting Reference Mode
15.2.4
Signal Mode
15.2.5
Expected Conversion Results
15.2.6
Interpreting Conversion Results
15.3
SOC Principle of Operation
15.3.1
SOC Configuration
15.3.2
Trigger Operation
15.3.2.1
Global Software Trigger
15.3.2.2
Trigger Repeaters
15.3.2.2.1
Oversampling Mode
15.3.2.2.2
Undersampling Mode
15.3.2.2.3
Trigger Phase Delay
15.3.2.2.4
Re-trigger Spread
15.3.2.2.5
Trigger Repeater Configuration
15.3.2.2.5.1
Register Shadow Updates
15.3.2.2.6
Re-Trigger Logic
15.3.2.2.7
Multi-Path Triggering Behavior
15.3.3
ADC Acquisition (Sample and Hold) Window
15.3.4
Sample Capacitor Reset
15.3.5
ADC Input Models
15.3.6
Channel Selection
15.3.6.1
External Channel Selection
15.3.6.1.1
External Channel Selection Timing
15.4
SOC Configuration Examples
15.4.1
Single Conversion from ePWM Trigger
15.4.2
Oversampled Conversion from ePWM Trigger
15.4.3
Multiple Conversions from CPU Timer Trigger
15.4.4
Software Triggering of SOCs
15.5
ADC Conversion Priority
15.6
Burst Mode
15.6.1
Burst Mode Example
15.6.2
Burst Mode Priority Example
15.7
EOC and Interrupt Operation
15.7.1
Interrupt Overflow
15.7.2
Continue to Interrupt Mode
15.7.3
Early Interrupt Configuration Mode
15.8
Post-Processing Blocks
15.8.1
PPB Offset Correction
15.8.2
PPB Error Calculation
15.8.3
PPB Result Delta Calculation
15.8.4
PPB Limit Detection and Zero-Crossing Detection
15.8.4.1
PPB Digital Trip Filter
15.8.5
PPB Sample Delay Capture
15.8.6
PPB Oversampling
15.8.6.1
Accumulation, Minimum, Maximum, and Average Functions
15.8.6.2
Outlier Rejection
15.9
Opens/Shorts Detection Circuit (OSDETECT)
15.9.1
Implementation
15.9.2
Detecting an Open Input Pin
15.9.3
Detecting a Shorted Input Pin
15.10
Power-Up Sequence
15.11
ADC Calibration
15.11.1
ADC Zero Offset Calibration
15.12
ADC Timings
15.12.1
ADC Timing Diagrams
15.12.2
Post-Processing Block Timings
15.13
Additional Information
15.13.1
Ensuring Synchronous Operation
15.13.1.1
Basic Synchronous Operation
15.13.1.2
Synchronous Operation with Multiple Trigger Sources
15.13.1.3
Synchronous Operation with Uneven SOC Numbers
15.13.1.4
Non-overlapping Conversions
15.13.2
Choosing an Acquisition Window Duration
15.13.3
Achieving Simultaneous Sampling
15.13.4
Result Register Mapping
15.13.5
Internal Temperature Sensor
15.13.6
Designing an External Reference Circuit
15.13.7
ADC-DAC Loopback Testing
15.13.8
Internal Test Mode
15.13.9
ADC Gain and Offset Calibration
15.14
Software
15.14.1
ADC Registers to Driverlib Functions
15.14.2
ADC Examples
15.14.2.1
ADC Software Triggering
15.14.2.2
ADC ePWM Triggering
15.14.2.3
ADC Temperature Sensor Conversion
15.14.2.4
ADC Synchronous SOC Software Force (adc_soc_software_sync)
15.14.2.5
ADC Continuous Triggering (adc_soc_continuous)
15.14.2.6
ADC Continuous Conversions Read by DMA (adc_soc_continuous_dma)
15.14.2.7
ADC PPB Offset (adc_ppb_offset)
15.14.2.8
ADC PPB Limits (adc_ppb_limits)
15.14.2.9
ADC PPB Delay Capture (adc_ppb_delay)
15.14.2.10
ADC ePWM Triggering Multiple SOC
15.14.2.11
ADC Burst Mode
15.14.2.12
ADC Burst Mode Oversampling
15.14.2.13
ADC SOC Oversampling
15.14.2.14
ADC PPB PWM trip (adc_ppb_pwm_trip)
15.14.2.15
ADC Trigger Repeater Oversampling
15.14.2.16
ADC Trigger Repeater Undersampling
15.15
ADC Registers
15.15.1
ADC Base Address Table
15.15.2
ADC_RESULT_REGS Registers
15.15.3
ADC_REGS Registers
16
Buffered Digital-to-Analog Converter (DAC)
16.1
Introduction
16.1.1
DAC Related Collateral
16.1.2
Features
16.1.3
Block Diagram
16.2
Using the DAC
16.2.1
Initialization Sequence
16.2.2
DAC Offset Adjustment
16.2.3
EPWMSYNCPER Signal
16.3
Lock Registers
16.4
Software
16.4.1
DAC Registers to Driverlib Functions
16.4.2
DAC Examples
16.4.2.1
Buffered DAC Enable
16.4.2.2
Buffered DAC Random
16.4.2.3
Buffered DAC Sine (buffdac_sine)
16.5
DAC Registers
16.5.1
DAC Base Address Table
16.5.2
DAC_REGS Registers
17
Comparator Subsystem (CMPSS)
17.1
Introduction
17.1.1
CMPSS Related Collateral
17.1.2
Features
17.1.3
Block Diagram
17.2
Comparator
17.3
Reference DAC
17.4
Ramp Generator
17.4.1
Ramp Generator Overview
17.4.2
Ramp Generator Behavior
17.4.3
Ramp Generator Behavior at Corner Cases
17.5
Digital Filter
17.5.1
Filter Initialization Sequence
17.6
Using the CMPSS
17.6.1
LATCHCLR, EPWMSYNCPER, and EPWMBLANK Signals
17.6.2
Synchronizer, Digital Filter, and Latch Delays
17.6.3
Calibrating the CMPSS
17.6.4
Enabling and Disabling the CMPSS Clock
17.7
CMPSS DAC Output
17.8
Software
17.8.1
CMPSS Registers to Driverlib Functions
17.8.2
CMPSS Examples
17.8.2.1
CMPSS Asynchronous Trip
17.8.2.2
CMPSS Digital Filter Configuration
17.9
CMPSS Registers
17.9.1
CMPSS Base Address Table
17.9.2
CMPSS_REGS Registers
18
Programmable Gain Amplifier (PGA)
18.1
Programmable Gain Amplifier (PGA) Overview
18.1.1
Features
18.1.2
Block Diagram
18.2
Linear Output Range
18.3
Gain Values
18.4
Modes of Operation
18.4.1
Buffer Mode
18.4.2
Standalone Mode
18.4.3
Non-inverting Mode
18.4.4
Subtractor Mode
18.5
External Filtering
18.5.1
Low-Pass Filter Using Internal Filter Resistor and External Capacitor
18.5.2
Single Pole Low-Pass Filter Using Internal Gain Resistor and External Capacitor
18.6
Error Calibration
18.6.1
Offset Error
18.6.2
Gain Error
18.7
Chopping Feature
18.8
Enabling and Disabling the PGA Clock
18.9
Lock Register
18.10
Analog Front-End Integration
18.10.1
Buffered DAC
18.10.2
Analog-to-Digital Converter (ADC)
18.10.2.1
Unfiltered Acquisition Window
18.10.2.2
Filtered Acquisition Window
18.10.3
Comparator Subsystem (CMPSS)
18.10.4
PGA_NEG_SHARED Feature
18.10.5
Alternate Functions
18.11
Examples
18.11.1
Non-Inverting Amplifier Using Non-Inverting Mode
18.11.2
Buffer Mode
18.11.3
Low-Side Current Sensing
18.11.4
Bidirectional Current Sensing
18.12
Software
18.12.1
PGA Registers to Driverlib Functions
18.12.2
PGA Examples
18.12.2.1
PGA DAC-ADC External Loopback Example
18.13
PGA Registers
18.13.1
PGA Base Address Table
18.13.2
PGA_REGS Registers
19
Enhanced Pulse Width Modulator (ePWM)
19.1
Introduction
19.1.1
EPWM Related Collateral
19.1.2
Submodule Overview
19.2
Configuring Device Pins
19.3
ePWM Modules Overview
19.4
Time-Base (TB) Submodule
19.4.1
Purpose of the Time-Base Submodule
19.4.2
Controlling and Monitoring the Time-Base Submodule
19.4.3
Calculating PWM Period and Frequency
19.4.3.1
Time-Base Period Shadow Register
19.4.3.2
Time-Base Clock Synchronization
19.4.3.3
Time-Base Counter Synchronization
19.4.3.4
ePWM SYNC Selection
19.4.4
Phase Locking the Time-Base Clocks of Multiple ePWM Modules
19.4.5
Simultaneous Writes to TBPRD and CMPx Registers Between ePWM Modules
19.4.6
Time-Base Counter Modes and Timing Waveforms
19.4.7
Global Load
19.4.7.1
Global Load Pulse Pre-Scalar
19.4.7.2
One-Shot Load Mode
19.4.7.3
One-Shot Sync Mode
19.5
Counter-Compare (CC) Submodule
19.5.1
Purpose of the Counter-Compare Submodule
19.5.2
Controlling and Monitoring the Counter-Compare Submodule
19.5.3
Operational Highlights for the Counter-Compare Submodule
19.5.4
Count Mode Timing Waveforms
19.6
Action-Qualifier (AQ) Submodule
19.6.1
Purpose of the Action-Qualifier Submodule
19.6.2
Action-Qualifier Submodule Control and Status Register Definitions
19.6.3
Action-Qualifier Event Priority
19.6.4
AQCTLA and AQCTLB Shadow Mode Operations
19.6.5
Configuration Requirements for Common Waveforms
19.7
Dead-Band Generator (DB) Submodule
19.7.1
Purpose of the Dead-Band Submodule
19.7.2
Dead-band Submodule Additional Operating Modes
19.7.3
Operational Highlights for the Dead-Band Submodule
19.8
PWM Chopper (PC) Submodule
19.8.1
Purpose of the PWM Chopper Submodule
19.8.2
Operational Highlights for the PWM Chopper Submodule
19.8.3
Waveforms
19.8.3.1
One-Shot Pulse
19.8.3.2
Duty Cycle Control
19.9
Trip-Zone (TZ) Submodule
19.9.1
Purpose of the Trip-Zone Submodule
19.9.2
Operational Highlights for the Trip-Zone Submodule
19.9.2.1
Trip-Zone Configurations
19.9.3
Generating Trip Event Interrupts
19.10
Event-Trigger (ET) Submodule
19.10.1
Operational Overview of the ePWM Event-Trigger Submodule
19.11
Digital Compare (DC) Submodule
19.11.1
Purpose of the Digital Compare Submodule
19.11.2
Enhanced Trip Action Using CMPSS
19.11.3
Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis
19.11.4
Operation Highlights of the Digital Compare Submodule
19.11.4.1
Digital Compare Events
19.11.4.2
Event Filtering
19.11.4.3
Valley Switching
19.12
ePWM Crossbar (X-BAR)
19.13
Applications to Power Topologies
19.13.1
Overview of Multiple Modules
19.13.2
Key Configuration Capabilities
19.13.3
Controlling Multiple Buck Converters With Independent Frequencies
19.13.4
Controlling Multiple Buck Converters With Same Frequencies
19.13.5
Controlling Multiple Half H-Bridge (HHB) Converters
19.13.6
Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
19.13.7
Practical Applications Using Phase Control Between PWM Modules
19.13.8
Controlling a 3-Phase Interleaved DC/DC Converter
19.13.9
Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
19.13.10
Controlling a Peak Current Mode Controlled Buck Module
19.13.11
Controlling H-Bridge LLC Resonant Converter
19.14
Register Lock Protection
19.15
High-Resolution Pulse Width Modulator (HRPWM)
19.15.1
Operational Description of HRPWM
19.15.1.1
Controlling the HRPWM Capabilities
19.15.1.2
HRPWM Source Clock
19.15.1.3
Configuring the HRPWM
19.15.1.4
Configuring High-Resolution in Deadband Rising-Edge and Falling-Edge Delay
19.15.1.5
Principle of Operation
19.15.1.5.1
Edge Positioning
19.15.1.5.2
Scaling Considerations
19.15.1.5.3
Duty Cycle Range Limitation
19.15.1.5.4
High-Resolution Period
19.15.1.5.4.1
High-Resolution Period Configuration
19.15.1.6
Deadband High-Resolution Operation
19.15.1.7
Scale Factor Optimizing Software (SFO)
19.15.1.8
HRPWM Examples Using Optimized Assembly Code
19.15.1.8.1
#Defines for HRPWM Header Files
19.15.1.8.2
Implementing a Simple Buck Converter
19.15.1.8.2.1
HRPWM Buck Converter Initialization Code
19.15.1.8.2.2
HRPWM Buck Converter Run-Time Code
19.15.1.8.3
Implementing a DAC Function Using an R+C Reconstruction Filter
19.15.1.8.3.1
PWM DAC Function Initialization Code
19.15.1.8.3.2
PWM DAC Function Run-Time Code
19.15.2
SFO Library Software - SFO_TI_Build_V8.lib
19.15.2.1
Scale Factor Optimizer Function - int SFO()
19.15.2.2
Software Usage
19.15.2.2.1
A Sample of How to Add "Include" Files
925
19.15.2.2.2
Declaring an Element
927
19.15.2.2.3
Initializing With a Scale Factor Value
929
19.15.2.2.4
SFO Function Calls
19.16
Software
19.16.1
EPWM Registers to Driverlib Functions
19.16.2
HRPWM Registers to Driverlib Functions
19.16.3
EPWM Examples
19.16.3.1
ePWM Trip Zone
19.16.3.2
ePWM Up Down Count Action Qualifier
19.16.3.3
ePWM Synchronization
19.16.3.4
ePWM Digital Compare
19.16.3.5
ePWM Digital Compare Event Filter Blanking Window
19.16.3.6
ePWM Valley Switching
19.16.3.7
ePWM Digital Compare Edge Filter
19.16.3.8
ePWM Deadband
19.16.3.9
ePWM DMA
19.16.3.10
ePWM Chopper
19.16.3.11
EPWM Configure Signal
19.16.3.12
Realization of Monoshot mode
19.16.3.13
EPWM Action Qualifier (epwm_up_aq)
19.16.4
HRPWM Examples
19.16.4.1
HRPWM Duty Control with SFO
19.16.4.2
HRPWM Slider
19.16.4.3
HRPWM Period Control
19.16.4.4
HRPWM Duty Control with UPDOWN Mode
19.16.4.5
HRPWM Slider Test
19.16.4.6
HRPWM Duty Up Count
19.16.4.7
HRPWM Period Up-Down Count
19.17
EPWM Registers
19.17.1
EPWM Base Address Table
19.17.2
EPWM_REGS Registers
20
Enhanced Capture (eCAP)
20.1
Introduction
20.1.1
Features
20.1.2
ECAP Related Collateral
20.2
Description
20.3
Configuring Device Pins for the eCAP
20.4
Capture and APWM Operating Mode
20.5
Capture Mode Description
20.5.1
Event Prescaler
20.5.2
Edge Polarity Select and Qualifier
20.5.3
Continuous/One-Shot Control
20.5.4
32-Bit Counter and Phase Control
20.5.5
CAP1-CAP4 Registers
20.5.6
eCAP Synchronization
20.5.6.1
Example 1 - Using SWSYNC with ECAP Module
20.5.7
Interrupt Control
20.5.8
DMA Interrupt
20.5.9
Shadow Load and Lockout Control
20.5.10
APWM Mode Operation
20.6
Application of the eCAP Module
20.6.1
Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
20.6.2
Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
20.6.3
Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
20.6.4
Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
20.7
Application of the APWM Mode
20.7.1
Example 1 - Simple PWM Generation (Independent Channels)
20.8
Software
20.8.1
ECAP Registers to Driverlib Functions
20.8.2
ECAP Examples
20.8.2.1
eCAP APWM Example
20.8.2.2
eCAP Capture PWM Example
20.8.2.3
eCAP APWM Phase-shift Example
20.9
ECAP Registers
20.9.1
ECAP Base Address Table
20.9.2
ECAP_REGS Registers
21
Enhanced Quadrature Encoder Pulse (eQEP)
21.1
Introduction
21.1.1
EQEP Related Collateral
21.2
Configuring Device Pins
21.3
Description
21.3.1
EQEP Inputs
21.3.2
Functional Description
21.3.3
eQEP Memory Map
21.4
Quadrature Decoder Unit (QDU)
21.4.1
Position Counter Input Modes
21.4.1.1
Quadrature Count Mode
21.4.1.2
Direction-Count Mode
21.4.1.3
Up-Count Mode
21.4.1.4
Down-Count Mode
21.4.2
eQEP Input Polarity Selection
21.4.3
Position-Compare Sync Output
21.5
Position Counter and Control Unit (PCCU)
21.5.1
Position Counter Operating Modes
21.5.1.1
Position Counter Reset on Index Event (QEPCTL[PCRM] = 00)
21.5.1.2
Position Counter Reset on Maximum Position (QEPCTL[PCRM] = 01)
21.5.1.3
Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
21.5.1.4
Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
21.5.2
Position Counter Latch
21.5.2.1
Index Event Latch
21.5.2.2
Strobe Event Latch
21.5.3
Position Counter Initialization
21.5.4
eQEP Position-compare Unit
21.6
eQEP Edge Capture Unit
21.7
eQEP Watchdog
21.8
eQEP Unit Timer Base
21.9
QMA Module
21.9.1
Modes of Operation
21.9.1.1
QMA Mode-1 (QMACTRL[MODE] = 1)
21.9.1.2
QMA Mode-2 (QMACTRL[MODE] = 2)
21.9.2
Interrupt and Error Generation
21.10
eQEP Interrupt Structure
21.11
Software
21.11.1
EQEP Registers to Driverlib Functions
21.11.2
EQEP Examples
21.11.2.1
Frequency Measurement Using eQEP
21.11.2.2
Position and Speed Measurement Using eQEP
21.11.2.3
Frequency Measurement Using eQEP via unit timeout interrupt
21.11.2.4
Motor speed and direction measurement using eQEP via unit timeout interrupt
21.12
EQEP Registers
21.12.1
EQEP Base Address Table
21.12.2
EQEP_REGS Registers
22
Serial Peripheral Interface (SPI)
22.1
Introduction
22.1.1
Features
22.1.2
SPI Related Collateral
22.1.3
Block Diagram
22.2
System-Level Integration
22.2.1
SPI Module Signals
22.2.2
Configuring Device Pins
22.2.2.1
GPIOs Required for High-Speed Mode
22.2.3
SPI Interrupts
22.2.4
DMA Support
22.3
SPI Operation
22.3.1
Introduction to Operation
22.3.2
Controller Mode
22.3.3
Peripheral Mode
22.3.4
Data Format
22.3.4.1
Transmission of Bit from SPIRXBUF
22.3.5
Baud Rate Selection
22.3.5.1
Baud Rate Determination
22.3.5.2
Baud Rate Calculation in Non-High Speed Mode (HS_MODE = 0)
22.3.6
SPI Clocking Schemes
22.3.7
SPI FIFO Description
22.3.8
SPI DMA Transfers
22.3.8.1
Transmitting Data Using SPI with DMA
22.3.8.2
Receiving Data Using SPI with DMA
22.3.9
SPI High-Speed Mode
22.3.10
SPI 3-Wire Mode Description
22.4
Programming Procedure
22.4.1
Initialization Upon Reset
22.4.2
Configuring the SPI
22.4.3
Configuring the SPI for High-Speed Mode
22.4.4
Data Transfer Example
22.4.5
SPI 3-Wire Mode Code Examples
22.4.5.1
3-Wire Controller Mode Transmit
1074
22.4.5.2.1
3-Wire Controller Mode Receive
1076
22.4.5.2.1
3-Wire Peripheral Mode Transmit
1078
22.4.5.2.1
3-Wire Peripheral Mode Receive
22.4.6
SPI STEINV Bit in Digital Audio Transfers
22.5
Software
22.5.1
SPI Registers to Driverlib Functions
22.5.2
SPI Examples
22.5.2.1
SPI Digital Loopback
22.5.2.2
SPI Digital Loopback with FIFO Interrupts
22.5.2.3
SPI Digital External Loopback without FIFO Interrupts
22.5.2.4
SPI Digital External Loopback with FIFO Interrupts
22.5.2.5
SPI Digital Loopback with DMA
22.5.2.6
SPI EEPROM
22.5.2.7
SPI DMA EEPROM
22.6
SPI Registers
22.6.1
SPI Base Address Table
22.6.2
SPI_REGS Registers
23
Serial Communications Interface (SCI)
23.1
Introduction
23.1.1
Features
23.1.2
SCI Related Collateral
23.1.3
Block Diagram
23.2
Architecture
23.3
SCI Module Signal Summary
23.4
Configuring Device Pins
23.5
Multiprocessor and Asynchronous Communication Modes
23.6
SCI Programmable Data Format
23.7
SCI Multiprocessor Communication
23.7.1
Recognizing the Address Byte
23.7.2
Controlling the SCI TX and RX Features
23.7.3
Receipt Sequence
23.8
Idle-Line Multiprocessor Mode
23.8.1
Idle-Line Mode Steps
23.8.2
Block Start Signal
23.8.3
Wake-Up Temporary (WUT) Flag
23.8.3.1
Sending a Block Start Signal
23.8.4
Receiver Operation
23.9
Address-Bit Multiprocessor Mode
23.9.1
Sending an Address
23.10
SCI Communication Format
23.10.1
Receiver Signals in Communication Modes
23.10.2
Transmitter Signals in Communication Modes
23.11
SCI Port Interrupts
23.11.1
Break Detect
23.12
SCI Baud Rate Calculations
23.13
SCI Enhanced Features
23.13.1
SCI FIFO Description
23.13.2
SCI Auto-Baud
23.13.3
Autobaud-Detect Sequence
23.14
Software
23.14.1
SCI Registers to Driverlib Functions
23.14.2
SCI Examples
23.14.2.1
Tune Baud Rate via UART Example
23.14.2.2
SCI FIFO Digital Loop Back
23.14.2.3
SCI Digital Loop Back with Interrupts
23.14.2.4
SCI Echoback
23.14.2.5
stdout redirect example
23.15
SCI Registers
23.15.1
SCI Base Address Table
23.15.2
SCI_REGS Registers
24
Universal Serial Bus (USB) Controller
24.1
Introduction
24.1.1
Features
24.1.2
USB Related Collateral
24.1.3
Block Diagram
24.1.3.1
Signal Description
24.1.3.2
VBus Recommendations
24.2
Functional Description
24.2.1
Operation as a Device
24.2.1.1
Control and Configurable Endpoints
24.2.1.1.1
IN Transactions as a Device
24.2.1.1.2
Out Transactions as a Device
24.2.1.1.3
Scheduling
24.2.1.1.4
Additional Actions
24.2.1.1.5
Device Mode Suspend
24.2.1.1.6
Start of Frame
24.2.1.1.7
USB Reset
24.2.1.1.8
Connect/Disconnect
24.2.2
Operation as a Host
24.2.2.1
Endpoint Registers
24.2.2.2
IN Transactions as a Host
24.2.2.3
OUT Transactions as a Host
24.2.2.4
Transaction Scheduling
24.2.2.5
USB Hubs
24.2.2.6
Babble
24.2.2.7
Host SUSPEND
24.2.2.8
USB RESET
24.2.2.9
Connect/Disconnect
24.2.3
DMA Operation
24.2.4
Address/Data Bus Bridge
24.3
Initialization and Configuration
24.3.1
Pin Configuration
24.3.2
Endpoint Configuration
24.4
USB Global Interrupts
24.5
Software
24.5.1
USB Registers to Driverlib Functions
24.5.2
USB Examples
24.5.2.1
USB CDC serial example
24.5.2.2
USB HID Mouse Device
24.5.2.3
USB Device Keyboard
24.5.2.4
USB Generic Bulk Device
24.5.2.5
USB HID Mouse Host
24.5.2.6
USB HID Keyboard Host
24.5.2.7
USB Mass Storage Class Host
24.5.2.8
USB Dual Detect
24.5.2.9
USB Throughput Bulk Device Example (usb_ex9_throughput_dev_bulk)
24.5.2.10
USB HUB Host example
24.6
USB Registers
24.6.1
USB Base Address Table
24.6.2
USB_REGS Registers
25
Fast Serial Interface (FSI)
25.1
Introduction
25.1.1
FSI Related Collateral
25.1.2
FSI Features
25.2
System-level Integration
25.2.1
CPU Interface
25.2.2
Signal Description
25.2.2.1
Configuring Device Pins
25.2.3
FSI Interrupts
25.2.3.1
Transmitter Interrupts
25.2.3.2
Receiver Interrupts
25.2.3.3
Configuring Interrupts
25.2.3.4
Handling Interrupts
25.2.4
CLA Task Triggering
25.2.5
DMA Interface
25.2.6
External Frame Trigger Mux
25.3
FSI Functional Description
25.3.1
Introduction to Operation
25.3.2
FSI Transmitter Module
25.3.2.1
Initialization
25.3.2.2
FSI_TX Clocking
25.3.2.3
Transmitting Frames
25.3.2.3.1
Software Triggered Frames
25.3.2.3.2
Externally Triggered Frames
25.3.2.3.3
Ping Frame Generation
25.3.2.3.3.1
Automatic Ping Frames
25.3.2.3.3.2
Software Triggered Ping Frame
25.3.2.3.3.3
Externally Triggered Ping Frame
25.3.2.3.4
Transmitting Frames with DMA
25.3.2.4
Transmit Buffer Management
25.3.2.5
CRC Submodule
25.3.2.6
Conditions in Which the Transmitter Must Undergo a Soft Reset
25.3.2.7
Reset
25.3.3
FSI Receiver Module
25.3.3.1
Initialization
25.3.3.2
FSI_RX Clocking
25.3.3.3
Receiving Frames
25.3.3.3.1
Receiving Frames with DMA
25.3.3.4
Ping Frame Watchdog
25.3.3.5
Frame Watchdog
25.3.3.6
Delay Line Control
25.3.3.7
Buffer Management
25.3.3.8
CRC Submodule
25.3.3.9
Using the Zero Bits of the Receiver Tag Registers
25.3.3.10
Conditions in Which the Receiver Must Undergo a Soft Reset
25.3.3.11
FSI_RX Reset
25.3.4
Frame Format
25.3.4.1
FSI Frame Phases
25.3.4.2
Frame Types
25.3.4.2.1
Ping Frames
25.3.4.2.2
Error Frames
25.3.4.2.3
Data Frames
25.3.4.3
Multi-Lane Transmission
25.3.5
Flush Sequence
25.3.6
Internal Loopback
25.3.7
CRC Generation
25.3.8
ECC Module
25.3.9
Tag Matching
25.3.10
User Data Filtering (UDATA Matching)
25.3.11
TDM Configurations
25.3.12
FSI Trigger Generation
25.3.13
FSI-SPI Compatibility Mode
25.3.13.1
Available SPI Modes
25.3.13.1.1
FSITX as SPI Controller, Transmit Only
25.3.13.1.1.1
Initialization
25.3.13.1.1.2
Operation
25.3.13.1.2
FSIRX as SPI Peripheral, Receive Only
25.3.13.1.2.1
Initialization
25.3.13.1.2.2
Operation
25.3.13.1.3
FSITX and FSIRX Emulating a Full Duplex SPI Controller
25.3.13.1.3.1
Initialization
25.3.13.1.3.2
Operation
25.4
FSI Programing Guide
25.4.1
Establishing the Communication Link
25.4.1.1
Establishing the Communication Link from the Main Device
25.4.1.2
Establishing the Communication Link from the Remote Device
25.4.2
Register Protection
25.4.3
Emulation Mode
25.5
Software
25.5.1
FSI Registers to Driverlib Functions
25.5.2
FSI Examples
25.5.2.1
FSI Loopback:CPU Control
25.5.2.2
FSI DMA frame transfers:DMA Control
25.5.2.3
FSI data transfer by external trigger
25.5.2.4
FSI data transfers upon CPU Timer event
25.5.2.5
FSI and SPI communication(fsi_ex6_spi_main_tx)
25.5.2.6
FSI and SPI communication(fsi_ex7_spi_remote_rx)
25.5.2.7
FSI P2Point Connection:Rx Side
25.5.2.8
FSI P2Point Connection:Tx Side
25.6
FSI Registers
25.6.1
FSI Base Address Table
25.6.2
FSI_TX_REGS Registers
25.6.3
FSI_RX_REGS Registers
26
Inter-Integrated Circuit Module (I2C)
26.1
Introduction
26.1.1
I2C Related Collateral
26.1.2
Features
26.1.3
Features Not Supported
26.1.4
Functional Overview
26.1.5
Clock Generation
26.1.6
I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
26.1.6.1
Formula for the Controller Clock Period
26.2
Configuring Device Pins
26.3
I2C Module Operational Details
26.3.1
Input and Output Voltage Levels
26.3.2
Selecting Pullup Resistors
26.3.3
Data Validity
26.3.4
Operating Modes
26.3.5
I2C Module START and STOP Conditions
26.3.6
Non-repeat Mode versus Repeat Mode
26.3.7
Serial Data Formats
26.3.7.1
7-Bit Addressing Format
26.3.7.2
10-Bit Addressing Format
26.3.7.3
Free Data Format
26.3.7.4
Using a Repeated START Condition
26.3.8
Clock Synchronization
26.3.9
Clock Stretching
26.3.10
Arbitration
26.3.11
Digital Loopback Mode
26.3.12
NACK Bit Generation
26.4
Interrupt Requests Generated by the I2C Module
26.4.1
Basic I2C Interrupt Requests
26.4.2
I2C FIFO Interrupts
26.5
Resetting or Disabling the I2C Module
26.6
Software
26.6.1
I2C Registers to Driverlib Functions
26.6.2
I2C Examples
26.6.2.1
C28x-I2C Library source file for FIFO interrupts
26.6.2.2
C28x-I2C Library source file for FIFO interrupts
26.6.2.3
C28x-I2C Library source file for FIFO using polling
26.6.2.4
I2C Digital Loopback with FIFO Interrupts
26.6.2.5
I2C EEPROM
26.6.2.6
I2C Digital External Loopback with FIFO Interrupts
26.6.2.7
I2C EEPROM
26.6.2.8
I2C controller target communication using FIFO interrupts
26.6.2.9
I2C EEPROM
26.6.2.10
I2C Extended Clock Stretching Controller TX
26.6.2.11
I2C Extended Clock Stretching Target RX
26.7
I2C Registers
26.7.1
I2C Base Address Table
26.7.2
I2C_REGS Registers
27
Power Management Bus Module (PMBus)
27.1
Introduction
27.1.1
PMBUS Related Collateral
27.1.2
Features
27.1.3
Block Diagram
27.2
Configuring Device Pins
27.3
Target Mode Operation
27.3.1
Configuration
27.3.2
Message Handling
27.3.2.1
Quick Command
27.3.2.2
Send Byte
27.3.2.3
Receive Byte
27.3.2.4
Write Byte and Write Word
27.3.2.5
Read Byte and Read Word
27.3.2.6
Process Call
27.3.2.7
Block Write
27.3.2.8
Block Read
27.3.2.9
Block Write-Block Read Process Call
27.3.2.10
Alert Response
27.3.2.11
Extended Command
27.3.2.12
Group Command
27.4
Controller Mode Operation
27.4.1
Configuration
27.4.2
Message Handling
27.4.2.1
Quick Command
27.4.2.2
Send Byte
27.4.2.3
Receive Byte
27.4.2.4
Write Byte and Write Word
27.4.2.5
Read Byte and Read Word
27.4.2.6
Process Call
27.4.2.7
Block Write
27.4.2.8
Block Read
27.4.2.9
Block Write-Block Read Process Call
27.4.2.10
Alert Response
27.4.2.11
Extended Command
27.4.2.12
Group Command
27.5
Software
27.5.1
PMBUS Registers to Driverlib Functions
27.6
PMBUS Registers
27.6.1
PMBUS Base Address Table
27.6.2
PMBUS_REGS Registers
28
Modular Controller Area Network (MCAN)
28.1
MCAN Introduction
28.1.1
MCAN Related Collateral
28.1.2
MCAN Features
28.2
MCAN Environment
28.3
CAN Network Basics
28.4
MCAN Integration
28.5
MCAN Functional Description
28.5.1
Module Clocking Requirements
28.5.2
Interrupt Requests
28.5.3
Operating Modes
28.5.3.1
Software Initialization
28.5.3.2
Normal Operation
28.5.3.3
CAN FD Operation
28.5.4
Transmitter Delay Compensation
28.5.4.1
Description
28.5.4.2
Transmitter Delay Compensation Measurement
28.5.5
Restricted Operation Mode
28.5.6
Bus Monitoring Mode
28.5.7
Disabled Automatic Retransmission (DAR) Mode
28.5.7.1
Frame Transmission in DAR Mode
28.5.8
Clock Stop Mode
28.5.8.1
Suspend Mode
28.5.8.2
Wakeup Request
28.5.9
Test Modes
28.5.9.1
External Loop Back Mode
28.5.9.2
Internal Loop Back Mode
28.5.10
Timestamp Generation
28.5.10.1
External Timestamp Counter
28.5.11
Timeout Counter
28.5.12
Safety
28.5.12.1
ECC Wrapper
28.5.12.2
ECC Aggregator
28.5.12.2.1
ECC Aggregator Overview
28.5.12.2.2
ECC Aggregator Registers
28.5.12.3
Reads to ECC Control and Status Registers
28.5.12.4
ECC Interrupts
28.5.13
Rx Handling
28.5.13.1
Acceptance Filtering
28.5.13.1.1
Range Filter
28.5.13.1.2
Filter for Specific IDs
28.5.13.1.3
Classic Bit Mask Filter
28.5.13.1.4
Standard Message ID Filtering
28.5.13.1.5
Extended Message ID Filtering
28.5.13.2
Rx FIFOs
28.5.13.2.1
Rx FIFO Blocking Mode
28.5.13.2.2
Rx FIFO Overwrite Mode
28.5.13.3
Dedicated Rx Buffers
28.5.13.3.1
Rx Buffer Handling
28.5.14
Tx Handling
28.5.14.1
Transmit Pause
28.5.14.2
Dedicated Tx Buffers
28.5.14.3
Tx FIFO
28.5.14.4
Tx Queue
28.5.14.5
Mixed Dedicated Tx Buffers/Tx FIFO
28.5.14.6
Mixed Dedicated Tx Buffers/Tx Queue
28.5.14.7
Transmit Cancellation
28.5.14.8
Tx Event Handling
28.5.15
FIFO Acknowledge Handling
28.5.16
Message RAM
28.5.16.1
Message RAM Configuration
28.5.16.2
Rx Buffer and FIFO Element
28.5.16.3
Tx Buffer Element
28.5.16.4
Tx Event FIFO Element
28.5.16.5
Standard Message ID Filter Element
28.5.16.6
Extended Message ID Filter Element
28.6
Software
28.6.1
MCAN Registers to Driverlib Functions
28.6.2
MCAN Examples
28.6.2.1
MCAN Internal Loopback with Interrupt
28.6.2.2
MCAN Loopback with Interrupts Example Using SYSCONFIG Tool
28.6.2.3
MCAN receive using Rx Buffer
28.6.2.4
MCAN External Reception (with mask filter) into RX-FIFO1
28.6.2.5
MCAN Classic frames transmission using Tx Buffer
28.6.2.6
MCAN External Reception (with RANGE filter) into RX-FIFO1
28.6.2.7
MCAN External Transmit using Tx Buffer
28.6.2.8
MCAN receive using Rx Buffer
28.6.2.9
MCAN Internal Loopback with Interrupt
28.6.2.10
MCAN External Transmit using Tx Buffer
28.6.2.11
MCAN Internal Loopback with Interrupt
28.7
MCAN Registers
28.7.1
MCAN Base Address Table
28.7.2
MCANSS_REGS Registers
28.7.3
MCAN_REGS Registers
28.7.4
MCAN_ERROR_REGS Registers
29
Local Interconnect Network (LIN)
29.1
LIN Overview
29.1.1
SCI Features
29.1.2
LIN Features
29.1.3
LIN Related Collateral
29.1.4
Block Diagram
29.2
Serial Communications Interface Module
29.2.1
SCI Communication Formats
29.2.1.1
SCI Frame Formats
29.2.1.2
SCI Asynchronous Timing Mode
29.2.1.3
SCI Baud Rate
29.2.1.3.1
Superfractional Divider, SCI Asynchronous Mode
29.2.1.4
SCI Multiprocessor Communication Modes
29.2.1.4.1
Idle-Line Multiprocessor Modes
29.2.1.4.2
Address-Bit Multiprocessor Mode
29.2.1.5
SCI Multibuffered Mode
29.2.2
SCI Interrupts
29.2.2.1
Transmit Interrupt
29.2.2.2
Receive Interrupt
29.2.2.3
WakeUp Interrupt
29.2.2.4
Error Interrupts
29.2.3
SCI DMA Interface
29.2.3.1
Receive DMA Requests
29.2.3.2
Transmit DMA Requests
29.2.4
SCI Configurations
29.2.4.1
Receiving Data
29.2.4.1.1
Receiving Data in Single-Buffer Mode
29.2.4.1.2
Receiving Data in Multibuffer Mode
29.2.4.2
Transmitting Data
29.2.4.2.1
Transmitting Data in Single-Buffer Mode
29.2.4.2.2
Transmitting Data in Multibuffer Mode
29.2.5
SCI Low-Power Mode
29.2.5.1
Sleep Mode for Multiprocessor Communication
29.3
Local Interconnect Network Module
29.3.1
LIN Communication Formats
29.3.1.1
LIN Standards
29.3.1.2
Message Frame
29.3.1.2.1
Message Header
29.3.1.2.2
Response
29.3.1.3
Synchronizer
29.3.1.4
Baud Rate
29.3.1.4.1
Fractional Divider
29.3.1.4.2
Superfractional Divider
29.3.1.4.2.1
Superfractional Divider In LIN Mode
29.3.1.5
Header Generation
29.3.1.5.1
Event Triggered Frame Handling
29.3.1.5.2
Header Reception and Adaptive Baud Rate
29.3.1.6
Extended Frames Handling
29.3.1.7
Timeout Control
29.3.1.7.1
No-Response Error (NRE)
29.3.1.7.2
Bus Idle Detection
29.3.1.7.3
Timeout After Wakeup Signal and Timeout After Three Wakeup Signals
29.3.1.8
TXRX Error Detector (TED)
29.3.1.8.1
Bit Errors
29.3.1.8.2
Physical Bus Errors
29.3.1.8.3
ID Parity Errors
29.3.1.8.4
Checksum Errors
29.3.1.9
Message Filtering and Validation
29.3.1.10
Receive Buffers
29.3.1.11
Transmit Buffers
29.3.2
LIN Interrupts
29.3.3
Servicing LIN Interrupts
29.3.4
LIN DMA Interface
29.3.4.1
LIN Receive DMA Requests
29.3.4.2
LIN Transmit DMA Requests
29.3.5
LIN Configurations
29.3.5.1
Receiving Data
29.3.5.1.1
Receiving Data in Single-Buffer Mode
29.3.5.1.2
Receiving Data in Multibuffer Mode
29.3.5.2
Transmitting Data
29.3.5.2.1
Transmitting Data in Single-Buffer Mode
29.3.5.2.2
Transmitting Data in Multibuffer Mode
29.4
Low-Power Mode
29.4.1
Entering Sleep Mode
29.4.2
Wakeup
29.4.3
Wakeup Timeouts
29.5
Emulation Mode
29.6
Software
29.6.1
LIN Registers to Driverlib Functions
29.6.2
LIN Examples
29.6.2.1
LIN Internal Loopback with Interrupts
29.6.2.2
LIN SCI Mode Internal Loopback with Interrupts
29.6.2.3
LIN SCI MODE Internal Loopback with DMA
29.6.2.4
LIN Internal Loopback without interrupts(polled mode)
29.6.2.5
LIN SCI MODE (Single Buffer) Internal Loopback with DMA
29.7
LIN Registers
29.7.1
LIN Base Address Table
29.7.2
LIN_REGS Registers
30
Configurable Logic Block (CLB)
30.1
Introduction
30.1.1
CLB Related Collateral
30.2
Description
30.2.1
CLB Clock
30.3
CLB Input/Output Connection
30.3.1
Overview
30.3.2
CLB Input Selection
30.3.3
CLB Output Selection
30.3.4
CLB Output Signal Multiplexer
30.4
CLB Tile
30.4.1
Static Switch Block
30.4.2
Counter Block
30.4.2.1
Counter Description
30.4.2.2
Counter Operation
30.4.2.3
Serializer Mode
30.4.2.4
Linear Feedback Shift Register (LFSR) Mode
30.4.3
FSM Block
30.4.4
LUT4 Block
30.4.5
Output LUT Block
30.4.6
Asynchronous Output Conditioning (AOC) Block
30.4.7
High Level Controller (HLC)
30.4.7.1
High Level Controller Events
30.4.7.2
High Level Controller Instructions
30.4.7.3
<Src> and <Dest>
30.4.7.4
Operation of the PUSH and PULL Instructions (Overflow and Underflow Detection)
30.5
CPU Interface
30.5.1
Register Description
30.5.2
Non-Memory Mapped Registers
30.6
DMA Access
30.7
CLB Data Export Through SPI RX Buffer
30.8
Software
30.8.1
CLB Registers to Driverlib Functions
30.8.2
CLB Examples
30.8.2.1
CLB Empty Project
30.8.2.2
CLB Combinational Logic
30.8.2.3
CLB GPIO Input Filter
30.8.2.4
CLB Auxilary PWM
30.8.2.5
CLB PWM Protection
30.8.2.6
CLB Event Window
30.8.2.7
CLB Signal Generator
30.8.2.8
CLB State Machine
30.8.2.9
CLB External Signal AND Gate
30.8.2.10
CLB Timer
30.8.2.11
CLB Timer Two States
30.8.2.12
CLB Interrupt Tag
30.8.2.13
CLB Output Intersect
30.8.2.14
CLB PUSH PULL
30.8.2.15
CLB Multi Tile
30.8.2.16
CLB Tile to Tile Delay
30.8.2.17
CLB Glue Logic
30.8.2.18
CLB based One-shot PWM
30.8.2.19
CLB AOC Control
30.8.2.20
CLB AOC Release Control
30.8.2.21
CLB XBARs
30.8.2.22
CLB AOC Control
30.8.2.23
CLB Serializer
30.8.2.24
CLB LFSR
30.8.2.25
CLB Lock Output Mask
30.8.2.26
CLB INPUT Pipeline Mode
30.8.2.27
CLB Clocking and PIPELINE Mode
30.8.2.28
CLB SPI Data Export
30.8.2.29
CLB SPI Data Export DMA
30.8.2.30
CLB Trip Zone Timestamp
30.8.2.31
CLB CRC
30.8.2.32
CLB TDM Serial Port
30.8.2.33
CLB LED Driver
30.9
CLB Registers
30.9.1
CLB Base Address Table
30.9.2
CLB_LOGIC_CONFIG_REGS Registers
30.9.3
CLB_LOGIC_CONTROL_REGS Registers
30.9.4
CLB_DATA_EXCHANGE_REGS Registers
31
Advanced Encryption Standard (AES) Accelerator
31.1
Introduction
31.1.1
AES Block Diagram
31.1.1.1
Interfaces
31.1.1.2
AES Subsystem
31.1.1.3
AES Wide-Bus Engine
31.1.2
AES Algorithm
31.2
AES Operating Modes
31.2.1
GCM Operation
31.2.2
CCM Operation
31.2.3
XTS Operation
31.2.4
ECB Feedback Mode
31.2.5
CBC Feedback Mode
31.2.6
CTR and ICM Feedback Modes
31.2.7
CFB Mode
31.2.8
F8 Mode
31.2.9
F9 Operation
31.2.10
CBC-MAC Operation
31.3
Extended and Combined Modes of Operations
31.3.1
GCM Protocol Operation
31.3.2
CCM Protocol Operation
31.3.3
Hardware Requests
31.4
AES Module Programming Guide
31.4.1
AES Low-Level Programming Models
31.4.1.1
Global Initialization
31.4.1.2
AES Operating Modes Configuration
31.4.1.3
AES Mode Configurations
31.4.1.4
AES Events Servicing
31.5
Software
31.5.1
AES Registers to Driverlib Functions
31.5.2
AES_SS Registers to Driverlib Functions
31.5.3
AES Examples
31.5.3.1
AES ECB Encryption Example
31.5.3.2
AES ECB De-cryption Example
31.5.3.3
AES GCM Encryption Example
31.5.3.4
AES GCM Decryption Example
31.5.3.5
AES CBC Encryption Example
31.5.3.6
AES CBC De-cryption Example
31.5.3.7
AES CMAC Authentication Example
31.6
AES Registers
31.6.1
AES Base Address Table
31.6.2
AES_REGS Registers
31.6.3
AES_SS_REGS Registers
32
Embedded Pattern Generator (EPG)
32.1
Introduction
32.1.1
Features
32.1.2
EPG Block Diagram
32.1.3
EPG Related Collateral
32.2
Clock Generator Modules
32.2.1
DCLK (50% duty cycle clock)
32.2.2
Clock Stop
32.3
Signal Generator Module
32.4
EPG Peripheral Signal Mux Selection
32.5
Application Software Notes
32.6
EPG Example Use Cases
32.6.1
EPG Example: Synchronous Clocks with Offset
32.6.1.1
Synchronous Clocks with Offset Register Configuration
32.6.2
EPG Example: Serial Data Bit Stream (LSB first)
32.6.2.1
Serial Data Bit Stream (LSB first) Register Configuration
32.6.3
EPG Example: Serial Data Bit Stream (MSB first)
32.6.3.1
Serial Data Bit Stream (MSB first) Register Configuration
32.7
EPG Interrupt
32.8
Software
32.8.1
EPG Registers to Driverlib Functions
32.8.2
EPG Examples
32.8.2.1
EPG Generating Synchronous Clocks
32.8.2.2
EPG Generating Two Offset Clocks
32.8.2.3
EPG Generating Two Offset Clocks With SIGGEN
32.8.2.4
EPG Generate Serial Data
32.8.2.5
EPG Generate Serial Data Shift Mode
32.9
EPG Registers
32.9.1
EPG Base Address Table
32.9.2
EPG_REGS Registers
32.9.3
EPG_MUX_REGS Registers
33
Revision History
4.8
Application Notes for Using the Bootloaders