SPRUJ59A April 2024 – September 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1
The F28P55x replaces a pair of VDDIO/VDD pins with GPIOs. When migrating from the F28003x it is necessary to disable the input buffer on the what was the VDD pin, so that the GPIO is not improperly driven(assuming the connection to VDD persists). The GPIOINENACTRL register disables the input buffer when cleared to 0. The default state at reset of this register is a 1, which enables the input buffer of the corresponding GPIO. The other GPIO can be safely connected to VDDIO, but if desired the input buffer can also be disabled on the corresponding GPIO if there are noise concerns in the system.
This address exists within the analog subsystem registers, which has a base address of 0x0005 D700. The GPIO input buffer control register (GPIOINENACTRL) has an offset of 0x132, within the analog subsystem base address.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | GPIO63 | R/W | 1h | One time configuration for GPIO63 to decide whether
Input buffer (INENA control) is enabled or disabled 0 - Input buffer is disabled 1 - Input buffer is enabled Reset type: XRSn |
2 | GPIO62 | R/W | 1h | One time configuration for GPIO62 to decide whether
Input buffer (INENA control) is enabled or disabled 0 - Input buffer is disabled 1 - Input buffer is enabled Reset type: XRSn |
1 | GPIO21 | R/W | 1h | One time configuration for GPIO21 to decide whether
Input buffer (INENA control) is enabled or disabled 0 - Input buffer is disabled 1 - Input buffer is enabled Reset type: XRSn |
0 | GPIO20 | R/W | 1h | One time configuration for GPIO20 to decide whether
Input buffer (INENA control) is enabled or disabled 0 - Input buffer is disabled 1 - Input buffer is enabled Reset type: XRSn |