SPRUJ59A April   2024  – September 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Feature Differences Between F28003x and F28P55x
    1. 1.1 F28003x and F28P55x Feature Comparison
  5. 2PCB Hardware Changes
    1. 2.1 PCB Hardware Changes for the 100-Pin PZ, 80-Pin PNA and 64-Pin PM Packages
    2. 2.2 100-Pin PZ, 80-Pin PNA and 64-Pin PM Migration Between F28003x and F28P55x For New and Existing PCB
    3. 2.3 GPIO Input Buffer Control Register
  6. 3Feature Differences for System Consideration
    1. 3.1 New Features in F28P55x
      1. 3.1.1 Programmable Gain Amplifier(PGA)
      2. 3.1.2 Universal Serial Bus (USB)
      3. 3.1.3 5V Failsafe IOs
      4. 3.1.4 Flash Write Protection
      5. 3.1.5 Neural-Network Processing Unit (NPU)
    2. 3.2 Communication Module Changes
    3. 3.3 Control Module Changes
    4. 3.4 Analog Module Differences
    5. 3.5 Other Device Changes
      1. 3.5.1 PLL
      2. 3.5.2 PIE Channel Mapping
      3. 3.5.3 Bootrom
      4. 3.5.4 SW Libraries Included in the ROM
      5. 3.5.5 AGPIO
    6. 3.6 Power Management
      1. 3.6.1 LDO/VREG
      2. 3.6.2 POR/BOR
      3. 3.6.3 Power Consumption
    7. 3.7 Memory Module Changes
    8. 3.8 GPIO Multiplexing Changes
    9. 3.9 Analog Multiplexing Changes
  7. 4Application Code Migration From F28003x to F28P55x
    1. 4.1 C2000Ware Header Files
    2. 4.2 Linker Command Files
    3. 4.3 C2000Ware Examples
  8. 5Specific Use Cases Related to F28P55x New Features
    1. 5.1 PGA
    2. 5.2 USB
  9. 6EABI Support
    1. 6.1 Flash API
  10. 7References
  11. 8Revision History

1.1 F28003x and F28P55x Feature Comparison

An overlaid block diagram of F28003x and F28P55x is shown in F28003x and F28P55x Overlaid Functional Block Diagram while feature comparison of the superset part numbers for the F28003x and F28P55x devices is shown in Table 1-1.

F28003x and F28P55x Overlaid Functional Block Diagram Figure 1-1 F28003x and F28P55x Overlaid Functional Block Diagram
Table 1-1 IP Differences
Feature F28003x F28P55x
CPU Frequency (MHz) 120 150
Fast Integer Division (FINTDIV) Yes No
Memory
Flash 384KB 1088KB
RAM Local Shared 32KB 64KB
Global Shared 32KB 64KB
System
Configurable Logic Block(CLB) 4 Tiles 2 Tiles
Motor Control Libraries in ROM Yes No
Background CRC(BGCRC) Yes No
HWBIST Yes No
Neural-Network Processing Unit (NNPU) No 1 - Type 0
Analog Peripherals
ADC 12-bit Number of ADCs 3 - Type 5 5 - Type 6
MSPS 4 4
Conversion Time (ns) 250 255
CMPSS 4 - Type 2 4 - Type 6
Buffered DAC - Type 2 2 1
Programmable Gain Amplifier (PGA) - 3 - Type 2
Output DAC from CMPSS DACL 0 1
Control Peripherals
eCAP/HRCAP Modules 3(1 with HRCAP capability) - Type 2 2 - Type 2
ePWM/HRPWM channels - Type 4 16 (8 with HRPWM) 24 (16 with HRPWM)
eQEP - Type2 2 3
Communication Periperhals
SDFM 8 - Type 2 -
CAN (DCAN) - Type 0 1 -
CANFD (MCAN) - Type 1 1 2
I2C 2 - Type 1 2 - Type 2
LIN - Type 1 2 1
HIC 1 - Type 1 -
PMBUS 1 - Type 1 1 - Type 2
SCI - Type 0 2 3
USB - 1 - Type 0
Table 1-2 100-pin IO and Analog Channel Counts
IO Type F28003x F28P55x
Digital
AIO (analog with digital inputs) 23 16
AGPIO (analog with digital inputs and outputs) 2 19
Additional GPIO 4 (2 from cJTAG and 2 from X1/X2) 4 (2 from cJTAG and 2 from X1/X2)
Standard GPIO 49 43
Total GPIO 55 66
Total GPIO + AIO 78 82
Analog
ADC Channels (single-ended) 23 35
Table 1-3 80-pin IO and Analog Channel Counts
IO Type F28003x F28P55x
Digital
AIO (analog with digital inputs) 16 12
AGPIO (analog with digital inputs and outputs) 2 16
Additional GPIO 4 (2 from cJTAG and 2 from X1/X2) 4 (2 from cJTAG and 2 from X1/X2)
Standard GPIO 37 32
Total GPIO 43 52
Total GPIO + AIO 59 64
Analog
ADC Channels (single-ended) 18 28
Table 1-4 64-pin IO and Analog Channel Counts
IO Type F28003x F28P55x
Digital
AIO (analog with digital inputs) 16 12
AGPIO (analog with digital inputs and outputs) 2 13
Additional GPIO 4 (2 from cJTAG and 2 from X1/X2) 4 (2 from cJTAG and 2 from X1/X2)
Standard GPIO 24 17
Total GPIO 30 37
Total GPIO + AIO 46 49
Analog
ADC Channels (single-ended) 16 28