SPRUJ60A April   2024  – October 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Feature Differences Between F280013x/15x and F28P55x
    1. 1.1 F280013x/15x and F28P55x Feature Comparison
  5. 2PCB Hardware Changes
    1. 2.1 PCB Hardware Changes for the 80-Pin PN/PNA, 64-Pin PM Packages
    2. 2.2 80-Pin PNA, 64-Pin PM Migration Between F280013x/15x and F28P55x For New and Existing PCB
  6. 3Feature Differences for System Consideration
    1. 3.1 New Features in F28P55x
      1. 3.1.1  Advance Encryption Standard (AES)
      2. 3.1.2  Universal Serial Bus (USB)
      3. 3.1.3  Configurable Logic Block (CLB)
      4. 3.1.4  Live Firmware Update (LFU)
      5. 3.1.5  Programmable Gain Amplifier (PGA)
      6. 3.1.6  ERAD
      7. 3.1.7  FSI
      8. 3.1.8  5V Failsafe IOs
      9. 3.1.9  Flash Write Protection
      10. 3.1.10 Neural-Network Processing Unit (NPU)
    2. 3.2 Communication Module Changes
    3. 3.3 Control Module Changes
    4. 3.4 Analog Module Differences
    5. 3.5 Other Device Changes
      1. 3.5.1 PLL
      2. 3.5.2 PIE Channel Mapping
      3. 3.5.3 Bootrom
    6. 3.6 Power Management
      1. 3.6.1 LDO/VREG
      2. 3.6.2 POR/BOR
      3. 3.6.3 Power Consumption
    7. 3.7 Memory Module Changes
    8. 3.8 GPIO Multiplexing Changes
    9. 3.9 Analog Multiplexing Changes
  7. 4Application Code Migration From F280013x/15x to F28P55x
    1. 4.1 C2000Ware Header Files
    2. 4.2 Linker Command Files
    3. 4.3 C2000Ware Examples
  8. 5Specific Use Cases Related to F28P55x New Features
    1. 5.1 AES
    2. 5.2 PGA
    3. 5.3 USB
  9. 6EABI Support
    1. 6.1 Flash API
  10. 7References
  11. 8Revision History

3.1.1 Advance Encryption Standard (AES)

The AES module provides hardware-accelerated data encryption and decryption operations based on a binary key. The AES is a symmetric cipher module that supports a 128-, 192-, or 256-bit key in hardware for encryption and decryption. The AES module is based on a symmetric algorithm, which means that the encryption and decryption keys are identical. To encrypt data means to convert it from plain text to an unintelligible form called cipher text. Decrypting cipher text converts previously encrypted data to its original plain text form. The main features of the AES accelerator are:

AES encrypt and decrypt operations are supported by:

  • Galois/Counter mode (GCM), with basic GHASH operation
  • Counter mode with CBC-MAC (CCM)
  • XTS mode

The following feedback operating modes are available:

  • Electronic code book mode (ECB)
  • Cipher block chaining mode (CBC)
  • Counter mode (CTR)
  • Cipher feedback mode (CFB), 128-bit
  • F8 mode
  • Key sizes: 128, 192, and 256 bits
  • Support for CBC_MAC and Fedora 9 (F9) authentication modes
  • Basic GHASH operation (when selecting no encryption)
  • Key scheduling in hardware
  • Support for µDMA transfers
  • Fully synchronous design