SPRUJ60A April   2024  – October 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Feature Differences Between F280013x/15x and F28P55x
    1. 1.1 F280013x/15x and F28P55x Feature Comparison
  5. 2PCB Hardware Changes
    1. 2.1 PCB Hardware Changes for the 80-Pin PN/PNA, 64-Pin PM Packages
    2. 2.2 80-Pin PNA, 64-Pin PM Migration Between F280013x/15x and F28P55x For New and Existing PCB
  6. 3Feature Differences for System Consideration
    1. 3.1 New Features in F28P55x
      1. 3.1.1  Advance Encryption Standard (AES)
      2. 3.1.2  Universal Serial Bus (USB)
      3. 3.1.3  Configurable Logic Block (CLB)
      4. 3.1.4  Live Firmware Update (LFU)
      5. 3.1.5  Programmable Gain Amplifier (PGA)
      6. 3.1.6  ERAD
      7. 3.1.7  FSI
      8. 3.1.8  5V Failsafe IOs
      9. 3.1.9  Flash Write Protection
      10. 3.1.10 Neural-Network Processing Unit (NPU)
    2. 3.2 Communication Module Changes
    3. 3.3 Control Module Changes
    4. 3.4 Analog Module Differences
    5. 3.5 Other Device Changes
      1. 3.5.1 PLL
      2. 3.5.2 PIE Channel Mapping
      3. 3.5.3 Bootrom
    6. 3.6 Power Management
      1. 3.6.1 LDO/VREG
      2. 3.6.2 POR/BOR
      3. 3.6.3 Power Consumption
    7. 3.7 Memory Module Changes
    8. 3.8 GPIO Multiplexing Changes
    9. 3.9 Analog Multiplexing Changes
  7. 4Application Code Migration From F280013x/15x to F28P55x
    1. 4.1 C2000Ware Header Files
    2. 4.2 Linker Command Files
    3. 4.3 C2000Ware Examples
  8. 5Specific Use Cases Related to F28P55x New Features
    1. 5.1 AES
    2. 5.2 PGA
    3. 5.3 USB
  9. 6EABI Support
    1. 6.1 Flash API
  10. 7References
  11. 8Revision History

1.1 F280013x/15x and F28P55x Feature Comparison

An overlaid block diagram of F280013x/15x and F28P55x is shown in Figure 1-1 while feature comparison of the superset part numbers for the F280013x/15x and F28P55x devices is shown in Table 1-1 .

F280013x/15x and F28P55x Overlaid Functional Block Diagram Figure 1-1 F280013x/15x and F28P55x Overlaid Functional Block Diagram
Table 1-1 IP Differences
Feature F280013x F280015x F28P55x
CPU Frequency (MHz) 120 120 150
Memory
Flash 256KB 256KB 1088KB
RAM Local Shared 32KB 32KB 64KB
Global Shared - - 64KB
System
Control Law Accelerator (CLA) - - 1
Configurable Logic Block (CLB) - - 2 Tiles
Motor Control Libraries in ROM Yes Yes No
ERAD - - 1 - Type 1
AES - - 1 - Type 0
LFU - - Yes
DMA - - Yes
Neural-Network Processing Unit (NNPU) - - 1 - Type 0
Analog Peripherals
ADC 12-bit Number of ADCs 2 - Type 5 2 - Type 5 5- Type 6
MSPS 4 4 4
Conversion Time (ns) 250 250 186.67
CMPSS 1 - Type
3		 1 - Type
5		 4 - Type
6
CMPSS_LITE 3 - Type 0 3 - Type 0 -
Buffered DAC - - 1 - Type 2
Programmable Gain Amplifier (PGA) - - 3 - Type 2
Output DAC from CMPSS DACL 1 1 1
Control Peripherals
eCAP/HRCAP Modules 2 - Type 2 3 - Type 2 2 - Type 2
ePWM/HRPWM channels - Type 4 14 (2 with HRPWM) 14 (4 with HRPWM) 24 (16 with HRPWM)
eQEP - Type 2 1 2 3
Communications Peripherals
CAN (DCAN) - Type 0 1 1 -
CANFD (MCAN) - Type 1 1 1 2
I2C 2 - Type 1 2 - Type 1 2 - Type 2
LIN - Type 1 - 1 1
PMBUS - 1 - Type 1 1 - Type 2
SCI - Type 0 3 3 3
FSI - - 1 - Type 2
USB - - 1- Type 0
Table 1-2 80-pin IO and Analog Channel Counts
IO Type F280015x F28P55x
Digital
AIO (analog with digital inputs) 10 12
AGPIO (analog with digital inputs and outputs) 11 16
Additional GPIO 4 (2 from cJTAG and 2 from X1/X2) 4 (2 from cJTAG and 2 from X1/X2)
Standard GPIO 37 32
Total GPIO 52 52
Total GPIO + AIO 62 64
Analog
ADC Channels (single-ended) 21 28
Table 1-3 64-pin IO and Analog Channel Counts
IO Type F280013x F280013xV/15x F28P55x
Digital
AIO (analog with digital inputs) 10 10 12
AGPIO (analog with digital inputs and outputs) 11 11 16
Additional GPIO 4 (2 from cJTAG and 2 from X1/X2) 4 (2 from cJTAG and 2 from X1/X2) 4 (2 from cJTAG and 2 from X1/X2)
Standard GPIO 23 22 17
Total GPIO 38 37 37
Total GPIO + AIO 48 47 49
Analog
ADC Channels (single-ended) 21 21 28