SPRUJ63A September   2022  – October 2023

 

  1.   1
  2.   Trademarks
  3. 1Introduction
    1. 1.1 EVM Revisions and Assembly Variants
    2. 1.2 Inside the Box
  4. 2Important Usage Notes
    1. 2.1 Power-On Usage Note
    2. 2.2 EMC, EMI, and ESD Compliance
  5. 3System Description
    1. 3.1 Key Features
    2. 3.2 Functional Block Diagram
    3. 3.3 Power-On/Off Procedures
      1. 3.3.1 Power-On Procedure
      2. 3.3.2 Power-Off Procedure
    4. 3.4 Peripheral and Major Component Description
      1. 3.4.1  Clocking
        1. 3.4.1.1 Ethernet PHY Clock
        2. 3.4.1.2 AM64x/AM243x Clock
        3. 3.4.1.3 PCIe Clock
      2. 3.4.2  Reset
      3. 3.4.3  Power
        1. 3.4.3.1 Power Input
        2. 3.4.3.2 Reverse Polarity Protection
        3. 3.4.3.3 Current Monitoring
        4. 3.4.3.4 Power Supply
        5. 3.4.3.5 Power Sequencing
        6. 3.4.3.6 AM64x/AM243x Power
      4. 3.4.4  Configuration
        1. 3.4.4.1 Boot Modes
      5. 3.4.5  JTAG
      6. 3.4.6  Test Automation
      7. 3.4.7  UART Interfaces
      8. 3.4.8  Memory Interfaces
        1. 3.4.8.1 DDR4 Interface
        2. 3.4.8.2 MMC Interfaces
          1. 3.4.8.2.1 Micro SD Interface
          2. 3.4.8.2.2 eMMC Interface
        3. 3.4.8.3 OSPI Interface
        4. 3.4.8.4 SPI EEPROM Interface
        5. 3.4.8.5 Board ID EEPROM Interface
      9. 3.4.9  Ethernet Interface
        1. 3.4.9.1 DP83867 PHY Default Configuration
        2. 3.4.9.2 DP83869 PHY Default Configuration
        3. 3.4.9.3 Ethernet LED
      10. 3.4.10 Display Interface
      11. 3.4.11 USB 2.0 Interface
      12. 3.4.12 PCIe Interface
      13. 3.4.13 High Speed Expansion Interface
      14. 3.4.14 CAN Interface
      15. 3.4.15 Interrupt
      16. 3.4.16 ADC Interface
      17. 3.4.17 Safety Connector
      18. 3.4.18 SPI Interfaces
      19. 3.4.19 I2C Interfaces
      20. 3.4.20 FSI Interface
  6. 4Known Issues and Modifications
    1. 4.1 Issue 1 - Embedded XDS110 Connection to AM64x Target in CCS
    2. 4.2 Issue 2 - DC Barrel Jack Warning when Hot-Plugging
    3. 4.3 Issue 3 - uSD Card Boot Not Working
  7. 5References
  8. 6Revision History

3.4.8.3 OSPI Interface

The EVM has 512 Mbit OSPI memory device of part number S28HS512TGABHM010 from Cypress is connected to OSPI0 interface of AM64x/AM243x SoC. The OSPI supports single and double data rates with memory speed up to 200MBps SDR and 400MBps DDR (200 MHz clock speed).

Two signals are routed to OSPI0_DQS:

  1. OSPI0_DQS from the memory device.
  2. OSPI0_LBCLK from SoC.

To route DQS from memory device, Mount R601 and R592 and DNI R600 and R591.

To route OSPI0_LBCLK from SoC, Mount R600 and R591 and DNI R601 and R592

Note: For more information, see the OSPI and QSPI Board Design and Layout Guidelines section in the AM64x Sitara™ Processors Data Manual.

OSPI and QSPI implementation: 0 Ω resistors are provided for DATA[7:0], DQS, INT# and CLK signals. Footprints to mount external pull up resistors are provided on DATA[7:0] to prevent bus floating. The footprint for the OSPI memory also allows the installation of either a QSPI memory or an OSPI memory. S25FL256SABHI200 from Cypress is used in variants where QSPI flash is required. The 0 ohm resistors used in pins OSPI_DATA[4:7] are removed if QSPI flash is mounted.

Note: For QSPI Configuration

Remove 0E resistors from the following

  1. OSPI_DQ4 to OSPI_DQ7 nets (R432, R441, R442, R443).
  2. OSPI_INTn (R158).

GUID-FA8DFAF9-D123-440F-A6C6-1E1C6BBE5962-low.pngFigure 3-17 AM64x/AM243x OSPI Interface