SPRUJ63A September   2022  – October 2023

 

  1.   1
  2.   Trademarks
  3. 1Introduction
    1. 1.1 EVM Revisions and Assembly Variants
    2. 1.2 Inside the Box
  4. 2Important Usage Notes
    1. 2.1 Power-On Usage Note
    2. 2.2 EMC, EMI, and ESD Compliance
  5. 3System Description
    1. 3.1 Key Features
    2. 3.2 Functional Block Diagram
    3. 3.3 Power-On/Off Procedures
      1. 3.3.1 Power-On Procedure
      2. 3.3.2 Power-Off Procedure
    4. 3.4 Peripheral and Major Component Description
      1. 3.4.1  Clocking
        1. 3.4.1.1 Ethernet PHY Clock
        2. 3.4.1.2 AM64x/AM243x Clock
        3. 3.4.1.3 PCIe Clock
      2. 3.4.2  Reset
      3. 3.4.3  Power
        1. 3.4.3.1 Power Input
        2. 3.4.3.2 Reverse Polarity Protection
        3. 3.4.3.3 Current Monitoring
        4. 3.4.3.4 Power Supply
        5. 3.4.3.5 Power Sequencing
        6. 3.4.3.6 AM64x/AM243x Power
      4. 3.4.4  Configuration
        1. 3.4.4.1 Boot Modes
      5. 3.4.5  JTAG
      6. 3.4.6  Test Automation
      7. 3.4.7  UART Interfaces
      8. 3.4.8  Memory Interfaces
        1. 3.4.8.1 DDR4 Interface
        2. 3.4.8.2 MMC Interfaces
          1. 3.4.8.2.1 Micro SD Interface
          2. 3.4.8.2.2 eMMC Interface
        3. 3.4.8.3 OSPI Interface
        4. 3.4.8.4 SPI EEPROM Interface
        5. 3.4.8.5 Board ID EEPROM Interface
      9. 3.4.9  Ethernet Interface
        1. 3.4.9.1 DP83867 PHY Default Configuration
        2. 3.4.9.2 DP83869 PHY Default Configuration
        3. 3.4.9.3 Ethernet LED
      10. 3.4.10 Display Interface
      11. 3.4.11 USB 2.0 Interface
      12. 3.4.12 PCIe Interface
      13. 3.4.13 High Speed Expansion Interface
      14. 3.4.14 CAN Interface
      15. 3.4.15 Interrupt
      16. 3.4.16 ADC Interface
      17. 3.4.17 Safety Connector
      18. 3.4.18 SPI Interfaces
      19. 3.4.19 I2C Interfaces
      20. 3.4.20 FSI Interface
  6. 4Known Issues and Modifications
    1. 4.1 Issue 1 - Embedded XDS110 Connection to AM64x Target in CCS
    2. 4.2 Issue 2 - DC Barrel Jack Warning when Hot-Plugging
    3. 4.3 Issue 3 - uSD Card Boot Not Working
  7. 5References
  8. 6Revision History

3.4.1.1 Ethernet PHY Clock

A clock generator of part number CDCLVC1310 is used to drive 25 MHz clock to the Ethernet PHYs. CDCLVC1310 is a 1:10 LVCMOS clock buffer, which takes 25 MHz crystal/LVCMOS reference input and provides ten 25 MHz LVCMOS clock outputs. The source for the clock buffer is either the CLKOUT0 pin from the SoC or a 25 MHz oscillator (ASFLMB-25.000MHZ-LY-T), the selection is made using a set of resistors. This selection can be made through the select lines of the clock buffer.

  1. IN_SEL0, IN_SEL1 = [00] for selecting CLKOUT0.
  2. IN_SEL0, IN_SEL1 = [01] for selecting oscillator input. This is the default condition.

The resistor termination for single ended Crystal input is provided as per device-specific data sheet.

Table 3-1 Source Clock Selection for the Clock Buffer
IN_SEL1IN_SEL0Clock ChosenMountUnmount
00EXT_REFCLK from SoCR40, R45R248, R253
10Oscillator inputR253, R40R45, R248
GUID-4D08D9C6-1EE3-4444-82C8-23B82C5C789D-low.pngFigure 3-4 AM64x/AM243x EVM Clock Tree
Note: Resistors that are marked with red color box are DNI.