SPRUJ66A February   2023  – December 2023

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1EVM Revisions and Assembly Variants
  5. 2Inside the Box
  6. 3EMC, EMI, and ESD Compliance
  7. 4System Description
    1. 4.1 Key Features
      1. 4.1.1 Processor
      2. 4.1.2 Power Supply
      3. 4.1.3 Memory
      4. 4.1.4 JTAG Emulator
      5. 4.1.5 Supported Interfaces and Peripherals
      6. 4.1.6 Expansion Connectors Headers to Support Application Specific Add On Boards
    2. 4.2 Functional Block Diagram
    3. 4.3 AM62A Low Power SK EVM Interface Mapping
    4. 4.4 Power ON/OFF Procedures
      1. 4.4.1 Power-On Procedure
      2. 4.4.2 Power-Off Procedure
      3. 4.4.3 Power Test Points
    5. 4.5 Peripheral and Major Component Description
      1. 4.5.1  Clocking
        1. 4.5.1.1 Peripheral Ref Clock
      2. 4.5.2  Reset
      3. 4.5.3  CSI Interface
      4. 4.5.4  Audio Codec Interface
      5. 4.5.5  HDMI Display Interface
      6. 4.5.6  JTAG Interface
      7. 4.5.7  Test Automation Header
      8. 4.5.8  UART Interface
      9. 4.5.9  USB Interface
        1. 4.5.9.1 USB 2 0 Type A Interface
        2. 4.5.9.2 USB 2 0 Type C Interface
      10. 4.5.10 Memory Interfaces
        1. 4.5.10.1 LPDDR4 Interface
        2. 4.5.10.2 OSPI Interface
        3. 4.5.10.3 MMC Interfaces
          1. 4.5.10.3.1 MMC0 - eMMC Interface
          2. 4.5.10.3.2 MMC1 - Micro SD Interface
          3. 4.5.10.3.3 MMC2 - M.2 Key E Interface
        4. 4.5.10.4 Board ID EEPROM
      11. 4.5.11 Ethernet Interface
        1. 4.5.11.1 CPSW Ethernet PHY Default Configuration
      12. 4.5.12 GPIO Port Expander
      13. 4.5.13 GPIO Mapping
      14. 4.5.14 Power
        1. 4.5.14.1 Power Requirements
        2. 4.5.14.2 Power Input
        3. 4.5.14.3 Power Supply
        4. 4.5.14.4 AM62A SoC Power
        5. 4.5.14.5 Current Monitoring
      15. 4.5.15 AM62A Low Power SK EVM User Setup and Configuration
        1. 4.5.15.1 Boot Modes
        2. 4.5.15.2 User Test LEDs
      16. 4.5.16 Expansion Headers
        1. 4.5.16.1 User Expansion Connector
        2. 4.5.16.2 MCU Connector
      17. 4.5.17 I2C Address Mapping
  8. 5Revision History

4.5.11 Ethernet Interface

The AM62A Low Power SK EVM offers two Ethernet Ports of 1 Gigabit Speed for external Communication.

RGMII1 and RGMII2 Gigabit Ethernet CPSW Port from AM62A SOC is connected to the On-Board PHY Transceiver DP83867.

CPSW_RGMII1and CPSW_RGMII2 Ports share a common MDIO Bus to communicate with the external PHY Transceiver.

Note: RGMII2 modular connector in E1 and E2 version EVM is descoped.
GUID-20221013-SS0I-JSWP-NSXQ-DSQCG2FWXRK0-low.png Figure 4-26 Ethernet Interface block diagram - Rev E1 and E2
GUID-20230831-SS0I-BRNR-V1BS-ZBWQK4KKDD99-low.png Figure 4-27 Ethernet Interface block diagram - Rev E3 and A