SPRUJ66A February   2023  – December 2023

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1EVM Revisions and Assembly Variants
  5. 2Inside the Box
  6. 3EMC, EMI, and ESD Compliance
  7. 4System Description
    1. 4.1 Key Features
      1. 4.1.1 Processor
      2. 4.1.2 Power Supply
      3. 4.1.3 Memory
      4. 4.1.4 JTAG Emulator
      5. 4.1.5 Supported Interfaces and Peripherals
      6. 4.1.6 Expansion Connectors Headers to Support Application Specific Add On Boards
    2. 4.2 Functional Block Diagram
    3. 4.3 AM62A Low Power SK EVM Interface Mapping
    4. 4.4 Power ON/OFF Procedures
      1. 4.4.1 Power-On Procedure
      2. 4.4.2 Power-Off Procedure
      3. 4.4.3 Power Test Points
    5. 4.5 Peripheral and Major Component Description
      1. 4.5.1  Clocking
        1. 4.5.1.1 Peripheral Ref Clock
      2. 4.5.2  Reset
      3. 4.5.3  CSI Interface
      4. 4.5.4  Audio Codec Interface
      5. 4.5.5  HDMI Display Interface
      6. 4.5.6  JTAG Interface
      7. 4.5.7  Test Automation Header
      8. 4.5.8  UART Interface
      9. 4.5.9  USB Interface
        1. 4.5.9.1 USB 2 0 Type A Interface
        2. 4.5.9.2 USB 2 0 Type C Interface
      10. 4.5.10 Memory Interfaces
        1. 4.5.10.1 LPDDR4 Interface
        2. 4.5.10.2 OSPI Interface
        3. 4.5.10.3 MMC Interfaces
          1. 4.5.10.3.1 MMC0 - eMMC Interface
          2. 4.5.10.3.2 MMC1 - Micro SD Interface
          3. 4.5.10.3.3 MMC2 - M.2 Key E Interface
        4. 4.5.10.4 Board ID EEPROM
      11. 4.5.11 Ethernet Interface
        1. 4.5.11.1 CPSW Ethernet PHY Default Configuration
      12. 4.5.12 GPIO Port Expander
      13. 4.5.13 GPIO Mapping
      14. 4.5.14 Power
        1. 4.5.14.1 Power Requirements
        2. 4.5.14.2 Power Input
        3. 4.5.14.3 Power Supply
        4. 4.5.14.4 AM62A SoC Power
        5. 4.5.14.5 Current Monitoring
      15. 4.5.15 AM62A Low Power SK EVM User Setup and Configuration
        1. 4.5.15.1 Boot Modes
        2. 4.5.15.2 User Test LEDs
      16. 4.5.16 Expansion Headers
        1. 4.5.16.1 User Expansion Connector
        2. 4.5.16.2 MCU Connector
      17. 4.5.17 I2C Address Mapping
  8. 5Revision History

4.5.7 Test Automation Header

AM62A Low Power SK EVM has a 40 pin test automation header (FH12A-40S-0.5SH) to allow an external controller to manipulate some basic operations like Power Down, POR, Warm Reset, Boot Mode control etc.

The Test Automation Circuit is powered by the 3.3V supply generated by a dedicated Always On regulator Mfr.Part# TPS62177DQCR. The SOC’s I2C1 instance is connected to the test automation header. Another I2C instance (BOOTMODE_I2C) from the Test Automation Header is connected to the 24 bit I2C boot mode IO Expander of Mfr. Part# TCA6424ARGJR to allow control of the boot modes for the AM62A SOC.

GUID-20221013-SS0I-NX0D-VFGF-J1BL00VGS1MZ-low.png Figure 4-16 Test Automation Interface block diagram

The test automation circuit has voltage translation circuits so that the controller is isolated from the IO voltages used by the AM62A. Boot mode for the AM62A can be user controlled by either using DIP Switches or the test automation header through the I2C IO Expander. Boot Mode Buffers are used to isolate the Boot Mode controls driven through DIP Switches or I2C IO Expander. The boot mode can be set using two 8-bit DIP switches on the board, which will connect a pull-up resistor to the output of a buffer when the switch is set to the ON position and to a weaker pull-down resistor when set to the OFF position. The output of the buffer is connected to the boot mode pins on the AM62A SOC and the output is enabled when the boot mode is needed during a reset cycle.

When boot mode is set through Test Automation header, the required switch values are set at the I2C IO expander output, which overwrites the DIP switch values to give the desired boot values to the SOC. The pins used for boot mode also have other functions which are automatically isolated by disabling the boot mode buffer during normal operation.

The power down signal from the Test automation header instructs the SKEVM to power down all the rails except for dedicated power supplies on the board. Similarly PORZn signal provides a hard reset to the SOC and WARM_RESETn for a warm reset to the SOC.

Pin no. Signal IO Direction Pin no. Signal IO Direction
1 VCC3V3_TA Power 21 NC NA
2 VCC3V3_TA Power 22 NC NA
3 VCC3V3_TA Power 23 NC NA
4 NC NA 24 NC NA
5 NC NA 25 DGND Power
6 NC NA 26 TEST_POWERDOWN Input
7 DGND Power 27 TEST_PORZn Input
8 NC NA 28 TEST_WARMRESETn Input
9 NC NA 29 NC NA
10 NC NA 30 TEST_GPIO1 Input
11 NC NA 31 TEST_GPIO2 Bidirectional
12 NC NA 32 TEST_GPIO3 Input
13 NC NA 33 TEST_GPIO4 Input
14 NC NA 34 DGND Power
15 NC NA 35 NC NA
16 DGND Power 36 SoC_I2C1_TA_SCL Bidirectional
17 NC NA 37 BOOTMODE_I2C_SCL Bidirectional
18 NC NA 38 SoC_I2C1_TA_SDA Bidirectional
19 NC NA 39 BOOTMODE_I2C_SDA Bidirectional
20 NC NA 40 DGND Power