SPRUJ66A February   2023  – December 2023

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1EVM Revisions and Assembly Variants
  5. 2Inside the Box
  6. 3EMC, EMI, and ESD Compliance
  7. 4System Description
    1. 4.1 Key Features
      1. 4.1.1 Processor
      2. 4.1.2 Power Supply
      3. 4.1.3 Memory
      4. 4.1.4 JTAG Emulator
      5. 4.1.5 Supported Interfaces and Peripherals
      6. 4.1.6 Expansion Connectors Headers to Support Application Specific Add On Boards
    2. 4.2 Functional Block Diagram
    3. 4.3 AM62A Low Power SK EVM Interface Mapping
    4. 4.4 Power ON/OFF Procedures
      1. 4.4.1 Power-On Procedure
      2. 4.4.2 Power-Off Procedure
      3. 4.4.3 Power Test Points
    5. 4.5 Peripheral and Major Component Description
      1. 4.5.1  Clocking
        1. 4.5.1.1 Peripheral Ref Clock
      2. 4.5.2  Reset
      3. 4.5.3  CSI Interface
      4. 4.5.4  Audio Codec Interface
      5. 4.5.5  HDMI Display Interface
      6. 4.5.6  JTAG Interface
      7. 4.5.7  Test Automation Header
      8. 4.5.8  UART Interface
      9. 4.5.9  USB Interface
        1. 4.5.9.1 USB 2 0 Type A Interface
        2. 4.5.9.2 USB 2 0 Type C Interface
      10. 4.5.10 Memory Interfaces
        1. 4.5.10.1 LPDDR4 Interface
        2. 4.5.10.2 OSPI Interface
        3. 4.5.10.3 MMC Interfaces
          1. 4.5.10.3.1 MMC0 - eMMC Interface
          2. 4.5.10.3.2 MMC1 - Micro SD Interface
          3. 4.5.10.3.3 MMC2 - M.2 Key E Interface
        4. 4.5.10.4 Board ID EEPROM
      11. 4.5.11 Ethernet Interface
        1. 4.5.11.1 CPSW Ethernet PHY Default Configuration
      12. 4.5.12 GPIO Port Expander
      13. 4.5.13 GPIO Mapping
      14. 4.5.14 Power
        1. 4.5.14.1 Power Requirements
        2. 4.5.14.2 Power Input
        3. 4.5.14.3 Power Supply
        4. 4.5.14.4 AM62A SoC Power
        5. 4.5.14.5 Current Monitoring
      15. 4.5.15 AM62A Low Power SK EVM User Setup and Configuration
        1. 4.5.15.1 Boot Modes
        2. 4.5.15.2 User Test LEDs
      16. 4.5.16 Expansion Headers
        1. 4.5.16.1 User Expansion Connector
        2. 4.5.16.2 MCU Connector
      17. 4.5.17 I2C Address Mapping
  8. 5Revision History

4.5.12 GPIO Port Expander

The I/O Expanders used in the AM62A Low Power SKEVM is a 24-Bit I2C based I/O Expander which is used for daughter cards plug-in detection and for generating resets and enable signals to various peripheral devices connected to it. The SoC_I2C1 bus of the AM62A SOC is used to interface with the I/O Expanders. The I2C device addresses of the I/O Expander are 0x21 and 0x23. See Table 10 below for the list of signals being controlled by the Expander.

IO EXPANDER - 01
Pin no SIGNAL DIRECTION PURPOSE
P00 NC - -
P01 GPIO_CPSW1_RST OUTPUT CPSW Ethernet PHY-1 Reset Control GPIO
P02 BT_EN_SOC OUTPUT M.2 Module Bluetooth Enable
P03 MMC1_SD_EN OUTPUT SD Card Load Switch Enable
P04 VPP_EN OUTPUT SOC eFuse Voltage(VPP=1.8V) Regulator Enable
P05 EXP_PS_3V3_EN OUTPUT EXP CONN 3.3V Power Switch Enable
P06 EXP_PS_5V0_EN OUTPUT EXP CONN 5V Power Switch Enable
P07 EXP_HAT_DETECT INPUT EXP CONN HAT Board Detection
P10 GPIO_AUD_RSTn OUTPUT Audio Codec Reset Control GPIO
P11 GPIO_eMMC_RSTn OUTPUT eMMC Reset control GPIO
P12 UART1_FET_BUF_EN OUTPUT SOC UART1 Mux Select
P13 BT_UART_WAKE_SOC_3V3 INPUT BT UART WKUP Signal
P14 GPIO_HDMI_RSTN OUTPUT HDMI Transmitter Reset Control GPIO
P15 CSI_GPIO0 NA CSI0 GPIO1
P16 CSI_GPIO1 NA CSI0 GPIO2
P17 WLAN_ALERTn INPUT M.2 Module WLAN Alert
P20 HDMI_INTN INPUT HDMI Interrupt
P21 TEST_GPIO2 INPUT TEST GPIO2 from Test Automation Connector
P22 MCASP1_FET_EN OUTPUT MCASP1 Enable and Direction Control
P23 MCASP1_BUF_BT_EN OUTPUT
P24 MCASP1_FET_SEL OUTPUT
P25 UART1_FET_SEL OUTPUT UART1 Mux/Demux Selection control
P26 PD_I2C_IRQ INPUT Interrupt Request from PD Controller
P27 IO_EXP_TEST_LED OUTPUT User Test LED 2
IO EXPANDER - 02
Pin no SIGNAL DIRECTION DEVICE
P10 WL_LT_EN OUTPUT M.2 Interface Level Translator Enable
P11 CSI_RSTZ OUTPUT CSI Reset control GPIO
P20 SPI0_FET_SEL OUTPUT SOC SPI0 MUX Selection
P21 SPI0_FET_OE OUTPUT SOC SPI0 MUX Enable
P22 GPIO_CPSW2_RST OUTPUT CPSW Ethernet PHY-2 Reset Control GPIO
P23 CSI_SEL2 OUTPUT CSI Mux/Demux Selection Control
P24 CSI_EN OUTPUT CSI Mux/Demux Enable
P25 AUTO_100M_1000M_CONFIG OUTPUT WLAN Reset control GPIO
P26 CSI_VLDO_SEL OUTPUT CSI I/O Voltage selection control (VCC_CSI_IO)
P27 SOC_WLAN_SDIO_RST OUTPUT M.2 Module WLAN/SDIO Reset