SPRUJ68 January   2023 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Inside the Box
    2. 1.2 Key Features and Interfaces
    3. 1.3 Thermal Compliance
    4. 1.4 EMC, DMI, and ESD Compliance
  4. 2User Interfaces
    1. 2.1 Power Input
      1. 2.1.1 Power Input [J22] With LED for Status [LD2]
      2. 2.1.2 Power Budget Considerations
    2. 2.2 User Inputs
      1. 2.2.1 Board Configuration Settings [SW1]
      2. 2.2.2 Reset Power Down Pushbutton [SW2]
      3. 2.2.3 User Pushbutton [SW3] With User LED Indication [LD3]
    3. 2.3 Standard Interfaces
      1. 2.3.1 Uart-Over-USB [J4 With LED for Status [LD1]
      2. 2.3.2 Gigabit Ethernet [J8] With Integrated LEDs for Status
      3. 2.3.3 JTAG Emulation Interface [J13]
      4. 2.3.4 USB3 1 Gen1 Interfaces [J9] [J11]
      5. 2.3.5 Stacked DisplayPort and HDMI Type A [J12]
      6. 2.3.6 M 2 Key M Connector [J21] for SSD Modules
      7. 2.3.7 MicroSD Card Cage [J19]
    4. 2.4 Expansion Interfaces
      1. 2.4.1 Heatsink [ACC1] With [J15] Fan Header
      2. 2.4.2 CAN-FD Connector(s) [J1] [J2] [J5] [J6]
      3. 2.4.3 Expansion Header [J3]
      4. 2.4.4 Camera Interface 22-Pin Flex Connectors [J16][J17]
      5. 2.4.5 Camera Interface 40-Pin High Speed [J20]
      6. 2.4.6 Automation and Control Connector [J24]
  5. 3Circuit Details
    1. 3.1 Top Level Diagram
    2. 3.2 AM68 SK EVM Interface Mapping
    3. 3.3 I2C Address Mapping
    4. 3.4 GPIO Mapping
    5. 3.5 I2C GPIO Expander Table
    6. 3.6 Identification EEPROM
  6. 4Revision History

2.4.3 Expansion Header [J3]

The EVM includes a 40-pin (2x20, 2.54mm pitch) expansion interface [J3]. The expansion connector supports variety of interfaces including: I2C, serial peripheral interface (SPI), I2S with Audio clock, UART, pulse width modulator (PWM), and GPIO. All signals on the interfaces are 3.3 V levels.

Table 2-9 Expansion Header Pin Definition [J3]
Pin # Pin Name Description(Processor Pin #) Dir
1 Power Power,3.3 V Output
2 Power Power,5.0 V Output
3 I2C_SDA I2CBus #4, Data (AF28) Bi-Dir
4 Power Power,5.0 V Output
5 I2C_SCL I2CBus #4, Clock (AD25) Bi-Dir
6 GND Ground
7 GP_CLK/GPIO REFCLK0/WKUP_GPIO0_66 (G25) Bi-Dir
8 UART_TXD UART#5 Transmit (W25) Output
9 GND Ground
10 UART_RXD UART#5 Receive (AC24) Input
11 GPIO GPIO0_42 (U24) Bi-Dir
12 I2S_SCLK McASP#1 ACLKX (AA24) Bi-Dir
13 GPIO GPIO0#36 (W24) Bi-Dir
14 GND Ground
15 GPIO WKUP_GPIO0_49 (K26) Bi-Dir
16 GPIO GPIO0#3 (AE28) Bi-Dir
17 Power Power,3.3V Output
18 GPIO AUDIO_EXT_REFCLK0(AD24) Bi-Dir
19 SPI_MOSI MCU SPI#0 Data 0 (E24) Bi-Dir
20 GND Ground
21 SPI_MISO MCU SPI#0 Data 1 (C28) Bi-Dir
22 GPIO WKUP_GPIO0_67 (J27) Bi-Dir
23 SPI_SCLK MCU SPI#0 Clock (D26) Bi-Dir
24 SPI_CS0 MCU SPI #0 Chip Select 0 (C27) Bi-Dir
25 GND Ground
26 SPI_CS1 MCU SPI #0 Chip Select 2 (D25) Bi-Dir
27 ID_SDA Wkup I2C Data (H27) Bi-Dir
28 ID_SCL Wkup I2C Clock (H24) Bi-Dir
29 GPIO WKUP_GPIO0_56 (G27) Bi-Dir
30 GND Ground
31 GPIO WKUP_GPIO0_57(J26) Bi-Dir
32 PWM0 PWM3_A (T25) Output
33 PWM1 PWM0_A (AE27) Output
34 GND Ground
35 I2S_FS McASP #1 FSX (V28) Bi-Dir
36 GPIO GPIO0_41 (T23) Bi-Dir
37 GPIO GPIO0_27 (V26) Bi-Dir
38 I2S_DIN McASP #1 (T28) Bi-Dir
39 GND Ground
40 I2S_DOUT McASP #1 (U25) Bi-Dir
Note: In the DIR column, output is to the expansion module, input is from the expansion module. Bi-Dir signals can be configured as either input or output.
Note: All processor signals on the Expansion connector can support other functions including GPIO. For full list of functions available on each pin, see the AM68 Processors Data Manual. Functions like UART and PWM set as INPUT or OUTPUT can be BI-DIR when configured as GPIO