SPRUJ68 January   2023 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Inside the Box
    2. 1.2 Key Features and Interfaces
    3. 1.3 Thermal Compliance
    4. 1.4 EMC, DMI, and ESD Compliance
  4. 2User Interfaces
    1. 2.1 Power Input
      1. 2.1.1 Power Input [J22] With LED for Status [LD2]
      2. 2.1.2 Power Budget Considerations
    2. 2.2 User Inputs
      1. 2.2.1 Board Configuration Settings [SW1]
      2. 2.2.2 Reset Power Down Pushbutton [SW2]
      3. 2.2.3 User Pushbutton [SW3] With User LED Indication [LD3]
    3. 2.3 Standard Interfaces
      1. 2.3.1 Uart-Over-USB [J4 With LED for Status [LD1]
      2. 2.3.2 Gigabit Ethernet [J8] With Integrated LEDs for Status
      3. 2.3.3 JTAG Emulation Interface [J13]
      4. 2.3.4 USB3 1 Gen1 Interfaces [J9] [J11]
      5. 2.3.5 Stacked DisplayPort and HDMI Type A [J12]
      6. 2.3.6 M 2 Key M Connector [J21] for SSD Modules
      7. 2.3.7 MicroSD Card Cage [J19]
    4. 2.4 Expansion Interfaces
      1. 2.4.1 Heatsink [ACC1] With [J15] Fan Header
      2. 2.4.2 CAN-FD Connector(s) [J1] [J2] [J5] [J6]
      3. 2.4.3 Expansion Header [J3]
      4. 2.4.4 Camera Interface 22-Pin Flex Connectors [J16][J17]
      5. 2.4.5 Camera Interface 40-Pin High Speed [J20]
      6. 2.4.6 Automation and Control Connector [J24]
  5. 3Circuit Details
    1. 3.1 Top Level Diagram
    2. 3.2 AM68 SK EVM Interface Mapping
    3. 3.3 I2C Address Mapping
    4. 3.4 GPIO Mapping
    5. 3.5 I2C GPIO Expander Table
    6. 3.6 Identification EEPROM
  6. 4Revision History

2.4.6 Automation and Control Connector [J24]

The EVM supports an interface to allow for automated control of the system, including functions like on/off, reset, and boot mode settings.

Table 2-14 Test Automation Interface Pin Definition [J24]
Pin Pin Name Description(Processor Pin #) Dir
1 Power Power,3.3 V Output
2 Power Power,3.3 V Output
3 Power Power,3.3 V Output
4-6 <open> N/A
7 GND Ground
8-15 <open> N/A
16 GND Ground
17-24 <open> N/A
25 GND Ground
26 POWERDOWNz EVM Power Down Input
27 PORz EVM Power-On/Cold Reset Input
28 RESETz EVM Warm Reset Input
29 <open> N/A
30 INT1z MCU_ADC1_AIN0 (P25) Input
31 INT2z MCU_ADC1_AIN1 (R25) Bi-Dir
32 <open> N/A
33 BOOTMODE_RSTz Bootmode Buffer Reset Input
34 GND Ground
35 <open> N/A
36 I2C_SCL MCU I2C Bus #0, Clock (G24) Bi-Dir
37 BOOTMODE_SCL Bootmode Buffer I2C Clock Input
38 I2C_SDA MCU I2C Bus #0, Data (J25) Bi-Dir
39 BOOTMODE_SDA Bootmode Buffer I2C Data Bi-Dir
40 GND Ground
41 GND Ground
42 GND Ground
Note: In the DIR column, output is to the test automation module, input is from the test automation module. Bi-Dir signals can be configured as either input or output.
Note: The signal polarity is identified with a trailing 'z' in the Pin Name, which indicates the signal is active LOW. For example, POWERDOWNz is an active low signal, meaning '0' = EVM is Powered Down, '1' = EVM is NOT Powered Down.