SPRUJ68 January   2023 AM68

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Inside the Box
    2. 1.2 Key Features and Interfaces
    3. 1.3 Thermal Compliance
    4. 1.4 EMC, DMI, and ESD Compliance
  4. 2User Interfaces
    1. 2.1 Power Input
      1. 2.1.1 Power Input [J22] With LED for Status [LD2]
      2. 2.1.2 Power Budget Considerations
    2. 2.2 User Inputs
      1. 2.2.1 Board Configuration Settings [SW1]
      2. 2.2.2 Reset Power Down Pushbutton [SW2]
      3. 2.2.3 User Pushbutton [SW3] With User LED Indication [LD3]
    3. 2.3 Standard Interfaces
      1. 2.3.1 Uart-Over-USB [J4 With LED for Status [LD1]
      2. 2.3.2 Gigabit Ethernet [J8] With Integrated LEDs for Status
      3. 2.3.3 JTAG Emulation Interface [J13]
      4. 2.3.4 USB3 1 Gen1 Interfaces [J9] [J11]
      5. 2.3.5 Stacked DisplayPort and HDMI Type A [J12]
      6. 2.3.6 M 2 Key M Connector [J21] for SSD Modules
      7. 2.3.7 MicroSD Card Cage [J19]
    4. 2.4 Expansion Interfaces
      1. 2.4.1 Heatsink [ACC1] With [J15] Fan Header
      2. 2.4.2 CAN-FD Connector(s) [J1] [J2] [J5] [J6]
      3. 2.4.3 Expansion Header [J3]
      4. 2.4.4 Camera Interface 22-Pin Flex Connectors [J16][J17]
      5. 2.4.5 Camera Interface 40-Pin High Speed [J20]
      6. 2.4.6 Automation and Control Connector [J24]
  5. 3Circuit Details
    1. 3.1 Top Level Diagram
    2. 3.2 AM68 SK EVM Interface Mapping
    3. 3.3 I2C Address Mapping
    4. 3.4 GPIO Mapping
    5. 3.5 I2C GPIO Expander Table
    6. 3.6 Identification EEPROM
  6. 4Revision History

2.4.4 Camera Interface 22-Pin Flex Connectors [J16][J17]

The EVM supports two (2) 22-pin flex (0.5mm pitch) connectors [J16][J17] for interfacing with camera modules. Each camera interface provides MIPI CSI-2interface (4Lane), Clock/Control signals, and power (3.3 V) to the camera.

To enable camera modules with same addressing to be used simultaneously, I2C mux is used to select each camera. The voltage level for Clock/Control signals is selectable between 1.8 V/3.3 V.

Table 2-10 Camera 1 Flex Pin Definition [J16]
Pin # Pin Name Description Dir
1/ 1A Power Power, 3.3V Output
3/ 2A I2C_SDA I2C Data # 1, Mux 0 Bi-Dir
5/ 3A I2C_SCL I2C Clock #1, Mux 0 Output
7/4A GND Ground
9/ 5A CAM0_AUX AUX (WKUP_GPIO0_88) Bi-Dir
11/ 6A CAM0_PWDN Pwr-Dwn(IO expander) Output
13/ 7A GND Ground
15/ 8A CSI0_D3_P CSIPort 0 Data Lane 3 Input
17/ 9A CSI0_D3_N CSIPort 0 Data Lane 3 Input
19/10A GND Ground
21/ 11A CSI0_D2_P CSIPort 0 Data Lane 0 Input
23 / 12A CSI0_D2_N CSIPort 0 Data Lane 0 Input
25 / 13A GND Ground
27 / 14A CSI0_CLK_P CSIPort 0 CLK Input
29 / 15A CSI0_CLK_N CSIPort 0 CLK Input
31 / 16A GND Ground
33 / 17A CSI0_D1_P CSIPort 0 Data Lane 1 Input
35 / 18A CSI0_D1_N CSIPort 0 Data Lane 1 Input
37 / 19A GND Ground
39 / 20A CSI0_D1_P CSIPort 0 Data Lane 0 Input
41 / 21A CSI0_D1_N CSIPort 0 Data Lane 0 Input
43 / 22A GND Ground
Table 2-11 Camera 2 Flex Pin Definition [J17]
Pin # PinName Description Dir
1/ 1A Power Power, 3.3V Output
3/ 2A I2C_SDA I2C Data # 1, Mux 1 Bi-Dir
5/ 3A I2C_SCL I2C Clock #1, Mux 1 Output
7/4A GND Ground
9/ 5A CAM1_AUX AUX (WKUP_GPIO0_70) Bi-Dir
11/ 6A CAM1_PWDN Pwr-Dwn(IO expander) Output
13/ 7A GND Ground
15/ 8A CSI1_D3_P CSIPort 1 Data Lane 3 Input
17/ 9A CSI1_D3_N CSIPort 1 Data Lane 3 Input
19/ 10A GND Ground
21/ 11A CSI1_D2_P CSIPort 1 Data Lane 0 Input
23 / 12A CSI1_D2_N CSIPort 1 Data Lane 0 Input
25 / 13A GND Ground
27 / 14A CSI1_CLK_P CSIPort 1 CLK Input
29 / 15A CSI1_CLK_N CSIPort 1 CLK Input
31 / 16A GND Ground
33 / 17A CSI1_D1_P CSIPort 1 Data Lane 1 Input
35 / 18A CSI1_D1_N CSIPort 1 Data Lane 1 Input
37 / 19A GND Ground
39 / 20A CSI1_D1_P CSIPort 1 Data Lane 0 Input
41 / 21A CSI1_D1_N CSIPort 1 Data Lane 0 Input
43 / 22A GND Ground
Note: In the DIR column, output is to the camera module, input is from the camera module. Bi-Dir signals can be configured as either input or output.