SPRUJ68 January   2023 AM68

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Inside the Box
    2. 1.2 Key Features and Interfaces
    3. 1.3 Thermal Compliance
    4. 1.4 EMC, DMI, and ESD Compliance
  4. 2User Interfaces
    1. 2.1 Power Input
      1. 2.1.1 Power Input [J22] With LED for Status [LD2]
      2. 2.1.2 Power Budget Considerations
    2. 2.2 User Inputs
      1. 2.2.1 Board Configuration Settings [SW1]
      2. 2.2.2 Reset Power Down Pushbutton [SW2]
      3. 2.2.3 User Pushbutton [SW3] With User LED Indication [LD3]
    3. 2.3 Standard Interfaces
      1. 2.3.1 Uart-Over-USB [J4 With LED for Status [LD1]
      2. 2.3.2 Gigabit Ethernet [J8] With Integrated LEDs for Status
      3. 2.3.3 JTAG Emulation Interface [J13]
      4. 2.3.4 USB3 1 Gen1 Interfaces [J9] [J11]
      5. 2.3.5 Stacked DisplayPort and HDMI Type A [J12]
      6. 2.3.6 M 2 Key M Connector [J21] for SSD Modules
      7. 2.3.7 MicroSD Card Cage [J19]
    4. 2.4 Expansion Interfaces
      1. 2.4.1 Heatsink [ACC1] With [J15] Fan Header
      2. 2.4.2 CAN-FD Connector(s) [J1] [J2] [J5] [J6]
      3. 2.4.3 Expansion Header [J3]
      4. 2.4.4 Camera Interface 22-Pin Flex Connectors [J16][J17]
      5. 2.4.5 Camera Interface 40-Pin High Speed [J20]
      6. 2.4.6 Automation and Control Connector [J24]
  5. 3Circuit Details
    1. 3.1 Top Level Diagram
    2. 3.2 AM68 SK EVM Interface Mapping
    3. 3.3 I2C Address Mapping
    4. 3.4 GPIO Mapping
    5. 3.5 I2C GPIO Expander Table
    6. 3.6 Identification EEPROM
  6. 4Revision History

2.3.3 JTAG Emulation Interface [J13]

The EVM supports JTAG emulation/debugger through a dedicated emulation connector [J13] on the baseboard. The connector is aligned with the Texas Instrument 20-pin CTI header standard (2x20, 1.27mm pitch), and is compatible with Texas Instruments modules (XDS110, XDS200, XDS560v2) and 3rd party modules.

Table 2-5 Expansion Header Pin Definition [J9]
Pin No. Pin Name Description (Processor Pin #) Dir
1 TMS Test Mode Select(TMS) Input
2 TRSTn Test Reset Input
3 TDI Test Data Input Input
4 TDIS Target Disconnect Output
5 Vref Target Voltage Detect, 3.3V Output
6 <No pin> No pin/Key
7 TDO Test Data Output Output
8 GND Ground
9 RTCK Test Clock Return Output
10 GND Ground
11 TCK Test Clock Input
12 GND Ground
13 EMU0 Emulation Pin 0 Bi-Dir
14 EMU1 Emulation Pin 1 Bi-Dir
15 RESETz Target Reset Input
16 GND Ground
17 Open
18 Open
19 Open
20 GND Ground
Note: In the DIR column, output is to the JTAG module, input is from the JTAG module. Bi-Dir signals can be configured as either input or output.